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參數資料
| 型號： | HY57V643220DSTP-6 |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | DRAM |
| 英文描述： | 4Banks x 512K x 32bits Synchronous DRAM |
| 中文描述： | 2M X 32 SYNCHRONOUS DRAM, 5.5 ns, PDSO86 |
| 封裝： | 0.400 X 0.875 INCH, 0.50 MM PITCH, LEAD FREE, TSOP2-86 |
| 文件頁數： | 10/13頁 |
| 文件大?。?/td> | 227K |
| 代理商： | HY57V643220DSTP-6 |
Rev. 0.3 / Sep. 2004
10
HY57V643220D(L/S)T(P) Series
4Banks x 512K x 32bits Synchronous DRAM
AC CHARACTERISTICS I
(AC operating conditions unless otherwise noted)
Note :
1. Assume t
R
/ t
F
(input rise and fall time) is 1ns. If t
R
& t
F
> 1ns, then [(t
R
+t
F
)/2-1]ns should be added to the parameter.
2. Access time to be measured with input signals of 1V/ns edge rate, from 0.8V to 2.0V. If t
R
> 1ns,
then (t
R
/2-0.5)ns should be added to the parameter.
Parameter
Symbol
45
5
55
6
7
Unit Note
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
System
Clock
Cycle Time
CAS
Latency=3
t
CK3
4.5
1000
5.0
1000
5.5
1000
6.0
1000
7.0
1000
ns
CAS
Latency=2
t
CK2
10
10
10
10
10
ns
Clock High Pulse Width
t
CHW
1.75
-
2.0
-
2.25
-
2.5
-
3.0
-
ns
1
Clock Low Pulse Width
t
CLW
1.75
-
2.0
-
2.25
-
2.5
-
3.0
-
ns
1
Access Time
From Clock
CAS
Latency=3
t
AC3
-
4.5
-
4.5
-
5.0
-
5.5
-
5.5
ns
2
CAS
Latency=2
t
AC2
-
6.0
-
6.0
-
6.0
-
6.0
-
6.0
ns
Data-out Hold Time
t
OH
1.5
-
1.5
-
2.0
-
2.0
-
2.0
-
ns
Data-Input Setup Time
t
DS
1.3
-
1.5
-
1.5
-
1.5
-
1.75
-
ns
1
Data-Input Hold Time
t
DH
0.8
-
1.0
-
1.0
-
1.0
-
1.0
-
ns
1
Address Setup Time
t
AS
1.3
-
1.5
-
1.5
-
1.5
-
1.75
-
ns
1
Address Hold Time
t
AH
0.8
-
1.0
-
1.0
-
1.0
-
1.0
-
ns
1
CKE Setup Time
t
CKS
1.3
-
1.5
-
1.5
-
1.5
-
1.75
-
ns
1
CKE Hold Time
t
CKH
0.8
-
1.0
-
1.0
-
1.0
-
1.0
-
ns
1
Command Setup Time
t
CS
1.3
-
1.5
-
1.5
-
1.5
-
1.75
-
ns
1
Command Hold Time
t
CH
0.8
-
1.0
-
1.0
-
1.0
-
1.0
-
ns
1
CLK to Data Output in
Low-Z Time
t
OLZ
1.0
-
1.0
-
1.0
-
1.0
-
1.0
-
ns
CLK to
Data Output
in High-Z Time
CAS
Latency=3
t
OHZ3
-
4.0
-
4.5
-
5.0
-
5.5
-
5.5
ns
CAS
Latency=2
t
OHZ2
-
6.0
-
6.0
-
6.0
-
6.0
-
6.0
ns
相關PDF資料 |
PDF描述 |
|---|---|
| HY57V643220DSTP-7 | 4Banks x 512K x 32bits Synchronous DRAM |
| HY57V643220DT-45 | 4Banks x 512K x 32bits Synchronous DRAM |
| HY57V643220DT-5 | 4Banks x 512K x 32bits Synchronous DRAM |
| HY57V643220DT-55 | 4Banks x 512K x 32bits Synchronous DRAM |
| HY57V643220DT-6 | 4Banks x 512K x 32bits Synchronous DRAM |
相關代理商/技術參數 |
參數描述 |
|---|---|
| HY57V643220DSTP-7 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:4Banks x 512K x 32bits Synchronous DRAM |
| HY57V643220DT-45 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:4Banks x 512K x 32bits Synchronous DRAM |
| HY57V643220DT-5 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:4Banks x 512K x 32bits Synchronous DRAM |
| HY57V643220DT-55 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:4Banks x 512K x 32bits Synchronous DRAM |
| HY57V643220DT-6 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:4Banks x 512K x 32bits Synchronous DRAM |
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