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參數(shù)資料
| 型號： | HY57V643220CT-8 |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | DRAM |
| 英文描述： | 4 Banks x 512K x 32Bit Synchronous DRAM |
| 中文描述： | 2M X 32 SYNCHRONOUS DRAM, 6 ns, PDSO86 |
| 封裝： | 0.400 X 0.875 INCH, 0.5 MM PITCH, TSOP2-86 |
| 文件頁數(shù)： | 8/12頁 |
| 文件大?。?/td> | 183K |
| 代理商： | HY57V643220CT-8 |
Rev. 0.8/Aug. 02
8
HY57V643220C
AC CHARACTERISTICS II
(AC operating conditions unless otherwise noted)
Note :
1. A new command can be given tRRC after self refresh exit
Parameter
Symbol
-47
-5
-55
-6
-7
-8
-P
-S
Unit
Note
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
RAS cycle time
Operation
tRC
51.7
-
55
-
55
-
60
-
63
-
64
-
70
-
70
-
ns
Auto Refresh
tRRC
51.7
-
55
-
55
-
60
-
63
-
64
-
70
-
70
-
ns
RAS to CAS delay
tRCD
14.1
-
15
-
16.5
-
18
-
20
-
20
-
20
-
20
-
ns
RAS active time
tRAS
37.6
100K
38.7
100
K
38.7
100
K
42
100
K
42
100
K
48
100
K
50
100
K
50
100
K
ns
RAS precharge time
tRP
14.1
-
15
-
16.5
-
18
-
20
-
20
-
20
-
20
-
ns
RAS to RAS bank active delay
tRRD
2
-
2
-
2
-
2
-
2
-
2
-
2
-
2
-
CLK
CAS to CAS delay
tCCD
1
-
1
-
1
-
1
-
1
-
1
-
1
-
1
-
CLK
Write command to data-in delay
tWTL
0
-
0
-
0
-
0
-
0
-
0
-
0
-
0
-
CLK
Data-in to precharge command
tDPL
1
-
1
-
1
-
1
-
1
-
1
-
1
-
1
-
CLK
Data-in to active command
tDAL
4
-
4
-
4
-
4
-
4
-
4
-
4
-
4
-
CLK
DQM to data-out Hi-Z
tDQZ
2
-
2
-
2
-
2
-
2
-
2
-
2
-
2
-
CLK
DQM to data-in mask
tDQM
0
-
0
-
0
-
0
-
0
-
0
-
0
-
0
-
CLK
MRS to new command
tMRD
2
-
2
-
2
-
2
-
2
-
2
-
2
-
2
-
CLK
Precharge to
data output Hi-Z
CAS Latency = 3 tPROZ3
3
-
3
-
3
-
3
-
3
-
3
-
3
-
3
-
CLK
CAS Latency = 2 tPROZ2
-
-
2
-
2
-
2
-
2
-
2
-
2
-
2
-
CLK
Power down exit time
tPDE
1
-
1
-
1
-
1
-
1
-
1
-
1
-
1
-
CLK
Self refresh exit time
tSRE
1
-
1
-
1
-
1
-
1
-
1
-
1
-
1
-
CLK
1
Refresh Time
tREF
-
64
-
64
-
64
-
64
-
64
-
64
-
64
-
64
ms
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HY57V643220CT-P | 4 Banks x 512K x 32Bit Synchronous DRAM |
| HY57V643220CT-S | 4 Banks x 512K x 32Bit Synchronous DRAM |
| HY57V643220CLT-5 | 4 Banks x 512K x 32Bit Synchronous DRAM |
| HY57V643220CLT-55 | 4 Banks x 512K x 32Bit Synchronous DRAM |
| HY57V643220CLT-6 | 4 Banks x 512K x 32Bit Synchronous DRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HY57V643220CT-I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2Mx32|3.3V|4K|5|SDR SDRAM - 64M |
| HY57V643220CT-P | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:4 Banks x 512K x 32Bit Synchronous DRAM |
| HY57V643220CT-S | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:4 Banks x 512K x 32Bit Synchronous DRAM |
| HY57V643220CT-SI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SDRAM|4X512KX32|CMOS|TSSOP|86PIN|PLASTIC |
| HY57V643220D | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:4Banks x 512K x 32bits Synchronous DRAM |
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