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    參數(shù)資料
    型號(hào): HY29F400BG55
    廠商: Hynix Semiconductor Inc.
    英文描述: 4 Megabit (512Kx8/256Kx16) 5 Volt-only Flash Memory
    中文描述: 4兆位(512Kx8/256Kx16)5伏只閃存
    文件頁數(shù): 2/40頁
    文件大?。?/td> 509K
    代理商: HY29F400BG55
    2
    Rev. 5.2/May 01
    HY29F400
    cessors. A 55 ns version operating over 5.0 volts
    ± 5% is also available. To eliminate bus conten-
    tion, the HY29F400 has separate chip enable
    (CE#), write enable (WE#) and output enable
    (OE#) controls.
    The device is compatible with the JEDEC single
    power-supply Flash command set standard. Com-
    mands are written to the command register using
    standard microprocessor write timings, from where
    they are routed to an internal state-machine that
    controls the erase and programming circuits.
    Device programming is performed a byte or word
    at a time by executing the four-cycle Program com-
    mand. This initiates an internal algorithm that au-
    tomatically times the program pulse widths and
    verifies proper cell margin.
    The HY29F400
    s sector erase architecture allows
    any number of array sectors to be erased and re-
    programmed without affecting the data contents
    of other sectors. Device erasure is initiated by
    executing the Erase command. This initiates an
    internal algorithm that automatically preprograms
    the array (if it is not already programmed) before
    executing the erase operation. During erase
    cycles, the device automatically times the erase
    pulse widths and verifies proper cell margin.
    To protect data in the device from accidental or
    unauthorized attempts to program or erase the
    BLOCK DIAGRAM
    device while it is in the system (e.g., by a virus),
    the device has a Sector Protect function which
    hardware write protects selected sectors. The
    sector protect and unprotect features can be en-
    abled in a PROM programmer. Temporary Sec-
    tor Unprotect, which requires a high voltage, al-
    lows in-system erasure and code changes in pre-
    viously protected sectors.
    Erase Suspend enables the user to put erase on
    hold for any period of time to read data from, or
    program data to, any sector that is not selected
    for erasure. True background erase can thus be
    achieved. The device is fully erased when shipped
    from the factory.
    Addresses and data needed for the programming
    and erase operations are internally latched during
    write cycles, and the host system can detect
    completion of a program or erase operation by
    observing the RY/BY# pin, or by reading the DQ[7]
    (Data# Polling) and DQ[6] (Toggle) status bits.
    Reading data from the device is similar to reading
    from SRAM or EPROM devices. Hardware data
    protection measures include a low V
    CC
    detector
    that automatically inhibits write operations during
    power transitions.
    The host can place the device into the standby
    mode. Power consumption is greatly reduced in
    this mode.
    STATE
    CONTROL
    WE#
    CE#
    OE#
    BYTE#
    COMMAND
    REGISTER
    DQ[15:0]
    A[17:0], A-1
    V
    CC
    DETECTOR
    TIMER
    ERASE VOLTAGE
    GENERATOR AND
    SECTOR SWITCHES
    PROGRAM
    VOLTAGE
    GENERATOR
    A
    X-DECODER
    Y-DECODER
    4 Mb FLASH
    MEMORY
    ARRAY
    Y-GATING
    DATA LATCH
    I/O BUFFERS
    I/O CONTROL
    RESET#
    DQ[15:0]
    A[17:0], A-1
    RY/BY#
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