參數(shù)資料
型號: HY27UF161G2M-TPCS
廠商: HYNIX SEMICONDUCTOR INC
元件分類: DRAM
英文描述: 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Memory
中文描述: 64M X 16 FLASH 3.3V PROM, 30 ns, PDSO48
封裝: 12 X 20 MM, 1.20 MM HEIGHT, LEAD FREE, TSOP1-48
文件頁數(shù): 21/48頁
文件大?。?/td> 476K
代理商: HY27UF161G2M-TPCS
Rev 0.7 / Apr. 2005
21
Preliminary
HY27UF(08/ 16)1G2M Series
HY27SF(08/ 16)1G2M Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
Parameter
Symbol
1.8Volt
3.3Volt
Unit
Min
Max
Min
Max
CLE Setup time
t
CLS
5
(2)
5
(2)
ns
CLE Hold time
t
CLH
15
(2)
15
(2)
ns
CE# setup time
t
CS
0
0
ns
CE# hold time
t
CH
10
10
ns
WE# pulse width
t
WP
40
(2)
40
(2)
ns
ALE setup time
t
ALS
5
(2)
5
(2)
ns
ALE hold time
t
ALH
15
(2)
15
(2)
ns
Data setup time
t
DS
25
(2)
25
(2)
ns
Data hold time
t
DH
15
15
ns
Write Cycle time
t
WC
60
(2)
60
(2)
ns
WE# High hold time
t
WH
20
20
ns
ALE to Data Loading time
tADL
100
100
ns
Data Transfer from Cell to register
t
R
27
(2)
27
(2)
us
ALE to RE# Delay (ID Read)
tAR
10
10
ns
CLE to RE# Delay
tCLR
10
10
ns
Ready to RE# Low
t
RR
20
20
ns
RE# Pulse Width
t
RP
25
(2)
25
(2)
ns
WE# High to Busy
t
WB
100
100
ns
Read Cycle Time
t
RC
60
(2)
60
(2)
ns
RE# Access Time
t
REA
30
30
ns
RE# High to Output High Z
t
RHZ
30
30
ns
CE# High to Output High Z
t
CHZ
20
20
ns
RE or CE High to Output hold
tOH
15
15
ns
RE# High Hold Time
t
REH
30
(2)
30
(2)
ns
Output High Z to RE# low
t
IR
0
0
ns
CE# Access Time
t
CEA
45
45
ns
WE# High to RE# low
t
WHR
60
60
ns
Device Resetting Time
(Read / Program / Erase)
t
RST
5/10/500
(1)
5/10/500
(1)
us
Table 13: AC Timing Characteristics
NOTE:
1. If Reset Command (FFh) is written at Ready state, the device goes into Busy for maximum 5us
2. These parameters are applied to the errata.
3. tADL is the time from the WE# rising edge of final address cycle to the WE# rising edge of first data cycle.
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