參數(shù)資料
型號(hào)： HY27SF161G2M-VIB
廠商： Hynix Semiconductor Inc.
英文描述： 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Memory
中文描述： 1Gbit的（128Mx8bit / 64Mx16bit）NAND閃存
文件頁(yè)數(shù)： 11/48頁(yè)
文件大?。?/td> 476K
代理商： HY27SF161G2M-VIB
Rev 0.7 / Apr. 2005
11
Preliminary
HY27UF(08/ 16)1G2M Series
HY27SF(08/ 16)1G2M Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
2. BUS OPERATION
There are six standard bus operations that control the device. These are Command Input, Address Input, Data Input,
Data Output, Write Protect, and Standby.
Typically glitches less than 5 ns on Chip Enable, Write Enable and Read Enable are ignored by the memory and do not
affect bus operations.
2.1 Command Input.
Command Input bus operation is used to give a command to the memory device. Command are accepted with Chip
Enable low, Command Latch Enable High, Address Latch Enable low and Read Enable High and latched on the rising
edge of Write Enable. Moreover for commands that starts a modifying operation (write/erase) the Write Protect pin
must be high. See figure 7 and table 13 for details of the timings requirements. Command codes are always applied on
IO7:0, disregarding the bus configuration (X8/X16).
2.2 Address Input.
Address Input bus operation allows the insertion of the memory address. To insert the 27 addresses(x8 device) needed
to access the 1Gbit 4 clock cycles are needed. Addresses are accepted with Chip Enable low, Address Latch Enable
High, Command Latch Enable low and Read Enable high and latched on the rising edge of Write Enable. Moreover for
commands that starts a modify operation (write/erase) the Write Protect pin must be high. See figure 8 and table 13
for details of the timings requirements. Addresses are always applied on IO7:0, disregarding the bus configuration
(X8/X16).
2.3 Data Input.
Data Input bus operation allows to feed to the device the data to be programmed. The data insertion is serially and
timed by the Write Enable cycles. Data are accepted only with Chip Enable low, Address Latch Enable low, Command
Latch Enable low, Read Enable High, and Write Protect High and latched on the rising edge of Write Enable. See figure
9 and table 13 for details of the timings requirements.
2.4 Data Output.
Data Output bus operation allows to read data from the memory array and to check the status register content, the
lock status and the ID data. Data can be serially shifted out toggling the Read Enable pin with Chip Enable low, Write
Enable High, Address Latch Enable low, and Command Latch Enable low. See figures 10,12,13 and table 13 for details
of the timings requirements.
2.5 Write Protect.
Hardware Write Protection is activated when the Write Protect pin is low. In this condition modify operation do not
start and the content of the memory is not altered. Write Protect pin is not latched by Write Enable to ensure the pro-
tection even during the power up.
2.6 Standby.
In Standby mode the device is deselected, outputs are disabled and Power Consumption is reduced.
相關(guān)PDF資料
PDF描述
HY27SF161G2M-VIP 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Memory
HY27UF161G2M-TIB 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Memory
HY27UF161G2M-TIP 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Memory
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HY27SF161G2M-VIP 制造商:HYNIX 制造商全稱(chēng):Hynix Semiconductor 功能描述:1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Memory
HY27SF161G2M-VIS 制造商:HYNIX 制造商全稱(chēng):Hynix Semiconductor 功能描述:1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Memory
HY27SF161G2M-VMB 制造商:HYNIX 制造商全稱(chēng):Hynix Semiconductor 功能描述:1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Memory
HY27SF161G2M-VMP 制造商:HYNIX 制造商全稱(chēng):Hynix Semiconductor 功能描述:1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Memory
HY27SF161G2M-VMS 制造商:HYNIX 制造商全稱(chēng):Hynix Semiconductor 功能描述:1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Memory
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