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參數(shù)資料
| 型號： | HV623 |
| 廠商： | ELAN Microelctronics Corp . |
| 英文描述： | 32-Channel 128-Level Amplitude Gray-Shade Display Column Driver(輸出電壓3～80V，32通道，128灰度級顯示器列驅(qū)動器) |
| 中文描述： | 32通道128級振幅灰色陰影顯示列驅(qū)動器（輸出電壓3?80V的，32通道，128灰度級顯示器列驅(qū)動器） |
| 文件頁數(shù)： | 4/10頁 |
| 文件大?。?/td> | 64K |
| 代理商： | HV623 |
12-125
Pin #
Name
Function
30-36
D1-D7
Inputs for binary-format parallel data.
26
SC (Shift Clock)
Triggers data on both rising and falling edges. This implies that the data rate is always twice the clock
rate (data rate = 20MHz max if clock rate = 10MHz max).
22
CSI (Chip
Select Input)
Input pin for the chip select pulse (when DIR is high).
Output pin for the chip select pulse (when DIR is low).
43
CSO (Chip
Select Output)
Input pin for the chip select pulse (when DIR is low).
Output pin for the chip select pulse (when DIR is high).
40
LC
Input for a pulse whose rising edge causes data from the input latches to enter the comparator latches,
and whose falling edge initiates the conversion of this binary data to an output level (D-to-A).
Also, the HV
OUT
will clear to zero after the load count is initiated.
CC (Count Clock) Input to the count clock generator whose increments are compared to the data in the comparator latches.
(Load Count)
42
18, 47
V
R
High-voltage ramp input for charging the output stage hold capacitors (C
H
).
This input can be linear or non-linear as desired.
28
DIR
When this pin is connected to V
DD
, input data is shifted in ascending order,
i.e., corresponding to HV
OUT
1 to HV
OUT
32. When connected to LVGND, input data is shifted
in descending order, i.e., corresponding to HV
OUT
32 to HV
OUT
1.
This is ground for the logic section.
HVGND and LVGND should be connected together externally.
27, 38
LVGND
17, 48
HVGND
This is ground for the high-voltage (output) section.
HVGND and LVGND should be connected together externally.
19, 45
V
PP
This input biases the output source followers.
1-16
49-64
HV
OUT
1-
HV
OUT
32
V
DD
(Analog)
V
DD
(Digital)
V
CTL
High-voltage outputs.
21
Low-voltage analog supply voltage.
29
Low-voltage digital supply voltage.
24
Voltage supply pin to prevent output voltage from being affected by its adjacent outputs (V
CTL
= 2V for a
particular panel). The combination of V
CTL
and R
CTL
will reduce the output voltage variation to less than
±
0.2V of delta voltage between high voltage outputs of the same level at all gray levels.
25
R
CTL
Current sense resistor to ground to prevent output voltage from being affected by its adjacent outputs
(R
CTL
= 56K
for a particular panel). See V
CTL
function above.
Pin Definitions
Input and Output Equivalent Circuits
V
DD
Input
GND
(Logic)
Logic Inputs
GND
(Logic)
Data Out
Logic Data Output
V
DD
HV623
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| HV62-300 | 制造商:CONNOR-WINFIELD 制造商全稱:Connor-Winfield Corporation 功能描述:HIGH FREQUENCY VCXO OSCILLATORS |
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