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參數(shù)資料
| 型號(hào)： | HV6008X |
| 廠商： | SUPERTEX INC |
| 元件分類： | 顯示驅(qū)動(dòng)器 |
| 英文描述： | 32-Channel 【40V Liquid Crystal Display Row Driver |
| 中文描述： | LIQUID CRYSTAL DISPLAY DRIVER, UUC48 |
| 封裝： | DIE |
| 文件頁數(shù)： | 1/5頁 |
| 文件大小： | 467K |
| 代理商： | HV6008X |
02/96/022
Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability
indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to
workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the
Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website.
32-Channel
±
40V Liquid Crystal Display Row Driver
Ordering Information
Features
Symmetrical
±
40V output swing
Active return to GND
15mA peak source/sink/GND current per channel
+5V control logic
Special shift register with clear
Phase shift control
Output enable
Data out enable
1MHz shift register
Surface mount package available
General Description
Not recommended for new designs.
The HV60 is a 32-channel liquid crystal display driver with 3-state
DMOS outputs. Each output can be set to +40V, -40V, or GND.
A symmetric waveform can be applied to a capacitive load using
the phase shift feature of the HV60.
The HV60 consists of a 32-bit shift register with Clear, Enable, and
Phase Shift logic, and 32 high voltage output buffers. With the
Enable pin held low, all outputs are placed in the return to zero
(GND) state. When Enable is high, each output reflects the data
in its shift register bit. All outputs with a logic “0” in their shift
register will be in the return to zero state. Outputs with a logic “1”
in their shift register will reflect the state of the phase shift pin.
These outputs will be switched to V
PP
when phase shift is high and
V
NN
when phase shift is logic “0”.
Additional functions provided are Shift Register Clear and Data
Out. All bits of the shift register are changed to logic “0” when Clear
is pulled low. With Clear at a logic “1”, normal shift register
operation proceeds. The data output reflects the status of the
32nd shift register stage.
Absolute Maximum Ratings
Supply voltage, V
DD11
Supply voltage, V
DD21
Supply voltage, V
PP1,2
Supply voltage, V
NN1,2
Logic input levels
1
-6V
+6V
+42V
-42V
V
DD1
- 0.3V to V
DD2
+ 0.3V
Ground currrent
2
700mA
Continuous total power dissipation
3
1W
Operating temperature range
-40
°
C to +85
°
C
Storage temperature range
-65
°
C to +150
°
C
Notes:
1. All voltages are referenced to GND.
2. Duty cycle is limited by the total power dissipated in the package.
3. For operation above 25
°
C ambient derate linearly to 85
°
C at 16.7mW/
°
C.
Package Options
Device
HV6008
HV6008PJ
HV6008DJ
HV6008PG
HV6008X
HV6008
44-J Lead Quad
Plastic Chip Carrier
44 -J Lead Quad
Ceramic Chip Carrier
44-Lead Quad Plastic
Gullwing
Die
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