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參數(shù)資料
| 型號： | HV574PG |
| 廠商： | SUPERTEX INC |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | 100 MHz, 80-Channel Serial To Parallel Converter With Push-Pull Outputs |
| 中文描述： | SIPO BASED PRPHL DRVR, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁數(shù)： | 2/5頁 |
| 文件大?。?/td> | 454K |
| 代理商： | HV574PG |
2
HV574
Electrical Characteristics
(over recommended commercial operating conditions unless noted)
DC Characteristics
Symbol
I
DD
Parameter
Min
Max
30
Units
mA
Conditions
V
DD
supply current
V
DD
= V
DD
max
f
CLK
= 25MHz
I
PP
Quiescent V
PP
supply current
100
μ
A
Outputs high
100
μ
A
Outputs low
I
DDQ
V
OH
Quiescent V
DD
supply current
High-level output
100
μ
A
All V
IN
= V
DD
I
O
= -30mA, V
PP
= 80V
I
O
= -100
μ
A
I
O
= 15mA, V
DD
= 5V
I
O
= 100
μ
A
V
IH
= V
DD
V
IL
= 0V
HV
OUT
Data out
V
PP
- 9V
V
DD
- 0.5
V
V
V
OL
Low-level output
HV
OUT
Data out
3.75
V
0.5
V
I
IH
I
IL
High-level logic input current
1.0
μ
A
Low-level logic input current
-1.0
μ
A
AC Characteristics
(T
A
= 85
°
C max. Logic signal inputs and Data inputs have t
r
, t
f
≤
5ns [10% and 90% points])
Symbol
Parameter
Min
Max
Units
Conditions
f
CLK
Clock frequency
0.001
25
MHz
V
DD
= 4.5V, T
J
= 25
°
C
V
DD
= 4.5V, T
J
= 125
°
C
0.001
20
t
WL
,t
WH
t
SU
t
H
t
ON
, t
OFF
t
DHL
t
DLH
t
DLE
*
t
WLE
t
SLE
tr, tf
Clock width high or low
20
ns
Data set-up time before clock rises
0
ns
Data hold time after clock rises
15
ns
Time from latch enable to HV
OUT
Delay time clock to data high to low
500
ns
C
L
= 15pF
C
L
= 15pF, V
DD
= 5.0V
C
L
= 15pF, V
DD
= 5.0V
38
ns
Delay time clock to data low to high
38
ns
Delay time clock to LE low to high
25
ns
Width of LE pulse
25
ns
LE set-up time before clock rises
0
ns
Output rise/fall time
1.0
μ
s
C
L
= 600pF,
HV
OUT
from 0 to 60V
*
t
DLE
is not required but is recommended to produce stable HV outputs and thus minimize power dissipation and current spikes (allows internal SR output to stabilize).
Symbol
Parameter
Min
Max
Units
V
DD
V
PP
V
IH
V
IL
f
CLK
T
A
Logic supply voltage
4.5
5.5
V
Output voltage
12
80
V
High-level input voltage
V
DD
-0.5V
0
V
Low-level input voltage
0.5
V
Clock frequency per register
0.001
25
MHz
Operating free-air temperature
-40
+85
°
C
Notes:
Power-up sequence should be the following:
1. Connect ground.
2. Apply V
DD
.
3. Set all inputs (Data, CLK, Enable, etc.) to a known state.
4. Apply V
PP
.
5. The V
PP
should not drop below V
DD
or float during operation.
Power-down sequence should be the reverse of the above.
The V
PP
should not drop below V
DD
during operation.
Recommended Operating Conditions
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| HV574PGG | 制造商:Supertex 功能描述:Shift Register/Latch/Driver Single 80-Bit Serial to Parallel 100-Pin PQFP |
| HV574PG-G | 功能描述:串行到并行邏輯轉(zhuǎn)換器 80V 80Ch Push-Pull RoHS:否 制造商:Supertex 工作電源電壓: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-32 封裝:Tray |
| HV574X | 制造商:SUPERTEX 制造商全稱:SUPERTEX 功能描述:100 MHz, 80-Channel Serial To Parallel Converter With Push-Pull Outputs |
| HV57708 | 制造商:SUPERTEX 制造商全稱:SUPERTEX 功能描述:32 MHz, 64-Channel Serial To Parallel Converter With Push-Pull Outputs |
| HV57708_07 | 制造商:SUPERTEX 制造商全稱:SUPERTEX 功能描述:32MHz, 64-Channel Serial to Parallel Converter with Push-Pull Outputs |
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