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參數(shù)資料
| 型號(hào)： | HV3922DJ |
| 廠商： | SUPERTEX INC |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | High Voltage PIN Diode Driver |
| 中文描述： | 4 CHANNEL, BUF OR INV BASED PRPHL DRVR, CQCC28 |
| 封裝： | 0.490 X 0.490 INCH, 0.190 INCH HEIGHT, 0.50 INCH PITCH, CERAMIC, MO-087AA, 28 PIN |
| 文件頁(yè)數(shù)： | 3/5頁(yè) |
| 文件大?。?/td> | 444K |
| 代理商： | HV3922DJ |
3
HV3922
Recommended Operating Conditions
Symbol
Parameter
Min
Max
Units
V
CC
V
IN
V
LL
V
PP
IP
D(N)
H
T
A
CL
Logic Supply Voltage
4.5
5.5
V
DC Logic Input Voltage
0
V
CC
-2.5
V
V
LL
Supply Voltage
V
PP
Supply Voltage
High-State Continuous P
D(N)
Source Current
Ambient Operating Temp
-3.5
V
200
220
V
1.7
mA
-55
+125
°
C
D
RV(N)
Load Capacitance
0
0.006
μ
F
Notes:
1.V
PP
rise time (dv/dt) should be less than 50V/
μ
S.
2.Power-up sequence should be the following:
A)
Connect ground;
B)
Apply V
CC
;
C)
Apply V
LL
;
D)
Apply V
PP
;
E)
Set all inputs to a known state. Power-down sequence should be the reverse of the above.
Function Table
Input
Output
Data
D
(N)
X
V
TH
Internal
Latch Q(N)
CS
ENA
OE
Level
2
P
D(N)
D
RV(N)
Fault
H
X
H
Pass
Previous State
Previous State
Previous State
VFH
X
H
H
X
Pass
Previous State
Previous State
Previous State
VFH
L
L
H
H
Pass
Set
Previous State
Previous State
VFH
L
L
H
L
Pass
Reset
Previous State
Previous State
VFH
L
L
H>L
H
P/F
Set
VDH
VDL
VFH
L
L
H>L
L
P/F
Reset
HI-Z
VDH
VFH
H
X
H>L
X
Previous State
P/F
Set
VDH
VDL
VFH
P/F
Reset
HI-Z
VDH
VFH
X
H
H>L
X
Previous State
Pass
Set
VDH
VDL
VFH
Pass
Reset
HI-Z
VDH
VFH
X
X
H
X
Fail
—
HI-Z
VDL
VFL
(At Power Up)
X
X
V
IH
X
P/F
Set
VDH
VDL
VFH
Notes:
1. X indicates “Don’t Care” input state (L or H).
2. The output threshold is internally tested for each P
D(N)
output; the pass condition occurs when OE = H and:
A) P
D(N)
driving high with output > V
TH (MAX)
, or may occurs if P
D(N)
driving high and output > V
TH (MIN)
and < V
TL (MAX)
.
OR
B) P
D(N)
driving Low with output < V
TH (MIN)
, or may occur if P
D(N)
driving low and output < V
TH (MAX)
and < V
TL (MIN)
.
The fail condition occurs when OE = H and conditions for “pass” are not satisfied.
3. Fault output = V
FL
indicates a fault has been detected in at least one of the P
D(N)
output loads when OE = H. All other outputs shall function normally when a fault
condition has been detected for one of the outputs. The Fault output shall remain in the low state, regardless of the state of the output which initiated the fault status, until
the next falling edge of OE. Whenever OE = L, the Fault output is forced to V
FH
, and the fault latch is reset. If the fault condition persists, the fault response repeats each
time the OE input is set to H.
4. H>L indicates falling edge (H to L).
5. HI-Z indicates no current is sourced to output P
D(N)
.
6. P/F indicates “Pass” or “Fail” fault threshold conditions.
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