- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄370709 > HT48RA0A(20SOP) MICROCONTROLLER|8-BIT|CMOS|SOP|20PIN|PLASTIC PDF資料下載
參數(shù)資料
| 型號： | HT48RA0A(20SOP) |
| 英文描述： | MICROCONTROLLER|8-BIT|CMOS|SOP|20PIN|PLASTIC |
| 中文描述： | 單片機(jī)| 8位|的CMOS |專科| 20針|塑料 |
| 文件頁數(shù)： | 12/42頁 |
| 文件大?。?/td> | 259K |
| 代理商： | HT48RA0A(20SOP) |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁當(dāng)前第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁
HT48R50A-1/HT48C50-1
Rev. 1.00
12
January 2, 2003
OSC1 and OSC2 are required. If the internal RC oscilla-
tor is used, the OSC1 and OSC2 can be selected as
general I/O lines or an 32768Hz crystal oscillator (RTC
OSC). Also, the frequencies of the internal RC oscillator
can be 3.2MHz, 1.6MHz, 800kHz and 400kHz (depends
on the options).
The WDT oscillator is a free running on-chip RC oscillator,
and no external components are required. Even if the sys-
tem enters the power down mode, the system clock is
stopped, but the WDT oscillator still works within a period
of 78 s. The WDT oscillator can be disabled by options to
conserve power.
Watchdog Timer
WDT
The WDT clock source is implemented by a dedicated
RC oscillator (WDT oscillator), RTC clock or instruction
clock (system clock divided by 4), determines the op-
tions. This timer is designed to prevent a software mal-
function or sequence from jumping to an unknown
location with unpredictable results. The Watchdog
Timer can be disabled by options. If the Watchdog Timer
is disabled, all the executions related to the WDT result
in no operation. The RTC clock is enabled only in the in-
ternal RC+RTC mode.
Once the internal WDT oscillator (RC oscillator with a
period of 65 s/5V normally) is selected, it is first divided
by 256 (8-stage) to get the nominal time-out period of
16.6ms/5V. This time-out period may vary with tempera-
tures, VDD and process variations. By invoking the
WDT prescaler, longer time-out periods can be realized.
Writing data to WS2, WS1, WS0 (bit 2,1,0 of the WDTS)
can give different time-out periods. If WS2, WS1, and
WS0 are all equal to 1, the division ratio is up to 1:128,
and the maximum time-out period is 2.2s/5V seconds. If
the WDT oscillator is disabled, the WDT clock may still
come from the instruction clock and operates in the
same manner except that in the HALT state the WDT
may stop counting and lose its protecting purpose. In
this situation the logic can only be restarted by external
logic. The high nibble and bit 3 of the WDTS are re-
served for user's defined flags, which can be used to in-
dicate some specified status.
If the device operates in a noisy environment, using the
on-chipRCoscillator(WDTOSC)or32kHzcrystaloscilla-
tor (RTC OSC) is strongly recommended, since the HALT
will stop the system clock.
WS2
WS1
WS0
Division Ratio
0
0
0
1:1
0
0
1
1:2
0
1
0
1:4
0
1
1
1:8
1
0
0
1:16
1
0
1
1:32
1
1
0
1:64
1
1
1
1:128
WDTS register
The WDT overflow under normal operation will initialize
chip reset and set the status bit TO . But in the HALT
mode, the overflow will initialize a warm reset and only
the PC and SP are reset to zero. To clear the contents of
WDT (including the WDT prescaler), three methods are
adopted;externalreset(alowleveltoRES),softwarein-
structionanda HALT instruction.Thesoftwareinstruc-
tion include
CLR WDT
and the other set
CLR
WDT1 and CLR WDT2 . Of these two types of instruc-
tion, only one can be active depending on the option
CLR WDT times selection option . If the CLR WDT is
selected (i.e. CLRWDT times equal one), any execution
of the CLR WDT instruction will clear the WDT. In the
case that CLR WDT1 and CLR WDT2 are chosen
(i.e. CLRWDT times equal two), these two instructions
must be executed to clear the WDT; otherwise, the WDT
may reset the chip as a result of time-out.
Power down operation
HALT
The HALT mode is initialized by the HALT instruction
and results in the following...
The system oscillator will be turned off but the WDT
oscillator remains running (if the WDT oscillator is se-
lected).
The contents of the on chip RAM and registers remain
unchanged.
WDT and WDT prescaler will be cleared and re-
counted again (if the WDT clock is from the WDT os-
cillator).
All of the I/O ports maintain their original status.
The PD flag is set and the TO flag is cleared.
The system can leave the HALT mode by means of an
external reset, an interrupt, an external falling edge sig-
&
!
*
= +
4 ; > # ! *
!
,
*
. ; > # ! *
!
4 ; ! ; *
,
* #
;
!
,
- ,
" ! #
!
,
*
Watchdog Timer
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HT48RA0A(24SOP) | MICROCONTROLLER|8-BIT|CMOS|SOP|24PIN|PLASTIC |
| HT48RA0A-20SOP | 8-BIT MICROCONTROLLER |
| HT48RA0A-24SOP | 8-BIT MICROCONTROLLER |
| HT48R11-2(18DIP-F0) | 8-BIT MICROCONTROLLER |
| HT48R11-2(20DIP-F0) | 8-BIT MICROCONTROLLER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HT48RA0A-24SOP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
| HT48RA1 | 制造商:HOLTEK 制造商全稱:Holtek Semiconductor Inc 功能描述:Remote Type 8-Bit MCU |
| HT48RA1_07 | 制造商:HOLTEK 制造商全稱:Holtek Semiconductor Inc 功能描述:Remote Type 8-Bit MCU |
| HT48RA1_09 | 制造商:HOLTEK 制造商全稱:Holtek Semiconductor Inc 功能描述:Remote Type 8-Bit MCU |
| HT48RA3 | 制造商:HOLTEK 制造商全稱:Holtek Semiconductor Inc 功能描述:HT48RA3/HT48CA3 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。