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參數(shù)資料
| 型號： | HT48RA0(20DIP-A) |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8-BIT MICROCONTROLLER |
| 中文描述： | 8位微控制器 |
| 文件頁數(shù)： | 9/42頁 |
| 文件大小： | 259K |
| 代理商： | HT48RA0(20DIP-A) |
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HT48R50A-1/HT48C50-1
Rev. 1.00
9
January 2, 2003
If the stack is full and a non-masked interrupt takes
place, the interrupt request flag will be recorded but the
acknowledge signal will be inhibited. When the stack
pointer is decremented (by RET or RETI), the interrupt
will be serviced. This feature prevents stack overflow al-
lowing the programmer to use the structure more easily.
In a similar case, if the stack is full and a CAL is subse-
quently executed, stack overflow occurs and the first en-
try will be lost (only the most recent 6 return addresses
are stored).
Data memory
RAM
The data memory is designed with 184 8 bits. The
data memory is divided into two functional groups: spe-
cial function registers and general purpose data mem-
ory (160 8). Most are read/write, but some are read
only.
The special function registers include the indirect ad-
dressing registers (00H, 02H), Timer/Event Counter 0
(TMR0;0DH), Timer/Event Counter 0 control register
(TMR0C;0EH), Timer/Event Counter 1 higher order
byte register (TMR1H;0FH), Timer/Event Counter 1
lower order byte register (TMR1L;10H), Timer/Event
Counter 1 control register (TMR1C;11H), program
counter lower-order byte register (PCL;06H), memory
pointer registers (MP0;01H, MP1;03H), accumulator
(ACC;05H), table pointer (TBLP;07H), table
higher-order byte register (TBLH;08H), status register
(STATUS;0AH), interrupt control register (INTC;0BH),
Watchdog Timer option setting register (WDTS;09H),
I/O registers (PA;12H, PB;14H, PC;16H, PD;18H,
PG;1EH) and I/O control registers (PAC;13H,
PBC;15H, PCC;17H, PDC;19H, PGC;1FH). The re-
maining space before the 60H is reserved for future ex-
panded usage and reading these locations will get
00H . The general purpose data memory, addressed
from 60H to FFH, is used for data and control informa-
tion under instruction commands.
All of the data memory areas can handle arithmetic,
logic, increment, decrement and rotate operations di-
rectly. Except for some dedicated bits, each bit in the
data memory can be set and reset by SET [m].i and
CLR [m].i . They are also indirectly accessible through
memory pointer registers (MP0 or MP1).
Indirect addressing register
Location 00H and 02H are indirect addressing registers
that are not physically implemented. Any read/write op-
eration of [00H] ([02H]) will access data memory pointed
to by MP0 (MP1). Reading location 00H (02H) itself indi-
rectly will return the result 00H. Writing indirectly results
in no operation.
The memory pointer registers (MP0 and MP1) are 8-bit
registers.
Accumulator
The accumulator is closely related to ALU operations. It
is also mapped to location 05H of the data memory and
can carry out immediate data operations. The data
movement between two data memory locations must
pass through the accumulator.
Arithmetic and logic unit
ALU
This circuit performs 8-bit arithmetic and logic operations.
The ALU provides the following functions:
Arithmetic operations (ADD, ADC, SUB, SBC, DAA)
Logic operations (AND, OR, XOR, CPL) Rotation (RL,
RR, RLC, RRC)
Increment and Decrement (INC, DEC)
Branch decision (SZ, SNZ, SIZ, SDZ ....)
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RAM mapping
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| HT48RA0-3 | 制造商:HOLTEK 制造商全稱:Holtek Semiconductor Inc 功能描述:Remote Type 8-Bit MCU |
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| HT48RA0A(20SOP) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MICROCONTROLLER|8-BIT|CMOS|SOP|20PIN|PLASTIC |
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