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參數(shù)資料
| 型號(hào)： | HT48R51-2(40DIP-A0) |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8-BIT MICROCONTROLLER |
| 中文描述： | 8位微控制器 |
| 文件頁(yè)數(shù)： | 18/42頁(yè) |
| 文件大?。?/td> | 259K |
| 代理商： | HT48R51-2(40DIP-A0) |
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HT48R50A-1/HT48C50-1
Rev. 1.00
18
January 2, 2003
The I/O functions of PB0/PB1 are shown below.
PB0 I/O
I
I
O
O
O
O
O
O
O
O
PB1 I/O
I
O
I
I
I
O
O
O
O
O
PB0 Mode
x
x
C
B
B
C
B
B
B
B
PB1 Mode
x
C
x
x
x
C
C
C
B
B
PB0 Data
x
x
D
0
1
D
0
0
1
0
1
PB1 Data
x
D
x
x
x
D
1
D
D
x
x
PB0 Pad Status
I
I
D
0
B
D
0
0
B
0
B
PB1 Pad Status
I
D
I
I
I
D
1
D
D
0
B
Note:
I input,
B buzzer option, BZ or BZ,
C CMOS output
O output,
D, D
0
, D
1
data,
x don't care
The PG0 is pin-shared with INT.
In case of Internal RC+I/O system oscillator, the PG1
and PG2 are pin-shared with OSC1 and OSC2 pins.
Once the Internal RC+I/O mode is selected, the PC3
and PC4 can be used as general purpose I/O lines. Oth-
erwise, the pull-high resistors and I/O functions of PG1
and PG2 will be disabled.
It is recommended that unused or not bonded out I/O
linesshouldbesetasoutputpinsbysoftwareinstruction
to avoid consuming power under input floating state.
Low voltage reset
LVR
The microcontroller provides low voltage reset circuit in
order to monitor the supply voltage of the device. If the
supply voltage of the device is within the range
0.9V~V
LVR
, such as changing a battery, the LVR will au-
tomatically reset the device internally.
The LVR includes the following specifications:
The low voltage (0.9V~V
LVR
) has to remain in their
original state to exceed 1ms. If the low voltage state
does not exceed 1ms, the LVR will ignore it and do not
perform a reset function.
The LVR uses the OR function with the external
RES signal to perform chip reset.
TherelationshipbetweenV
DD
andV
LVR
isshownbelow.
Note:
V
OPR
is the voltage range for proper chip opera-
tion at 4MHz system clock.
2 F 2
1 F 1
F +
F 5
(
2 F 2
2 F 2
(
F 5
! *
#
!
G
G
*
"
! #
!
(
*
!
! *
!
Low voltage reset
Note:
*1: To make sure that the system oscillator has stabilized, the SST provides an extra delay of
1024 system clock pulses before entering the normal operation.
*2: Since low voltage has to be maintained in its original state and exceed 1ms, therefore 1ms
delay enters the reset mode.
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