參數(shù)資料
型號(hào): HT47C10L
英文描述: 8-Bit R-F Type Low Voltage Mask MCU
中文描述: 8位低電壓RF型微控制器面具
文件頁(yè)數(shù): 8/38頁(yè)
文件大?。?/td> 287K
代理商: HT47C10L
HT47C10L
Rev. 1.10
8
October 2, 2002
pointer is decremented (by RET or RETI), the interrupt
will be serviced. This feature prevents stack overflow al-
lowing the programmer to use the structure more easily.
In a similar case, if the stack is full and a CALL is sub-
sequently executed, stack overflow occurs and the first
entry will be lost (only the most recent two return ad-
dresses is stored).
Data memory
RAM
The data memory is designed with 54 8 bits. The data
memory is divided into two functional groups: special
functionregistersandgeneral-purposedatamemory(32 8).
Most are read/write, but some are read only.
Thespecialfunctionregistersincludetheindirectaddress-
ing register 0 (00H), the memory pointer register 0 (MP0;
01H),theindirectaddressingregister1(02H),thememory
pointer register 1 (MP1;03H), the bank pointer (BP;04H),
the accumulator (ACC;05H), the program counter
lower-order byte register (PCL;06H), the table pointer
(TBLP;07H), the table higher-order byte register
(TBLH;08H),thetimebasecontrolregister(TBC;09H),the
status register (STATUS;0AH), the interrupt control regis-
ter 0 (INTC;0BH), the I/O registers (PA;12H), I/O port con-
trol register (PAC;13H), the timer/event counter A
higher-order byte register (TMRAH; 20H), the timer/event
counter A lower-order byte register (TMRAL; 21H), the
timer/event counter control register (TMRC; 22H), the
timer/event counter B higher-order byte register (TMRBH;
23H), the timer/event counter B lower-order byte register
(TMRBL; 24H), the RC oscillator type A/D converter con-
trol register (ADCR; 25H) and the option register (OPT1;
26H, OPT2; 27H).
Theremainingspacebeforethe60Harereservedforfu-
ture expanded usage and reading these location will re-
turn the result 00H. The general-purpose data memory,
addressed from 60H to 7FH, is used for data and control
information under instruction command.
All data memory areas can handle arithmetic, logic, in-
crement, decrement and rotate operations. Except for
some dedicated bits, each bit in the data memory can be
set and reset by the SET [m].i and CLR [m].i instruction,
respectively. They are also indirectly accessible through
memory pointer registers (MP0;01H, MP1;03H).
Indirect addressing register
Location 00H and 02H are indirect addressing registers
that are not physically implemented. Any read/write op-
eration of [00H] and [02H] access data memory pointed
to by MP0 (01H) and MP1 (03H) respectively. Reading
location 00H or 02H indirectly will return the result 00H.
Writing indirectly results in no operation.
The function of data movement between two indirect ad-
dressing registers are not supported. The memory
pointer registers, MP0 and MP1, are both 8-bit registers
which can be used to access the data memory by com-
bining corresponding indirect addressing registers.
MP0 only can be applied to data memory, while MP1
can be applied to data memory and LCD display mem-
ory.
Accumulator
The accumulator is closely related to ALU operations. It
is also mapped to location 05H of the data memory and
is capable of carrying out immediatedataoperations.The
data movement between two data memory locations
must pass through the accumulator.
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RAM mapping (bank 0)
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