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參數(shù)資料
| 型號： | HT46R47(18SOP-A) |
| 英文描述： | Analog IC |
| 中文描述： | 模擬IC |
| 文件頁數(shù)： | 14/45頁 |
| 文件大小： | 297K |
| 代理商： | HT46R47(18SOP-A) |
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HT46R47
Rev. 1.40
14
July 18, 2001
Reset
Therearethreewaysinwhicharesetcanoccur:
RES reset during normal operation
RES reset during HALT
WDT time-out reset during normal operation
The WDT time-out during HALT is different
from other chip reset conditions, since it can
perform a warm reset that resets only the PC
and SP, leaving the other circuits in their origi-
nal state. Some registers remain unchanged
during other reset conditions. Most registers
are reset to the initial condition when the re-
set conditions are met. By examining the PD
and TO flags, the program can distinguish be-
tween different chip resets .
TO PD
RESET Conditions
0
0
RES reset during power-up
u
u
RES reset during normal operation
0
1
RES wake-up HALT
1
u
WDT time-out during normal opera-
tion
1
1
WDT wake-up HALT
Note: u means unchanged
To guarantee that the system oscillator is
started and stabilized, the SST (System
Start-up Timer) provides an extra-delay of
1024systemclockpulseswhenthesystemreset
(power-up, WDT time-out or RES reset) or the
system awakes from the HALT state.
When a system reset occurs, the SST delay is
added during the reset period. Any wake-up
from HALT will enable the SST delay.
The functional unit chip reset status are shown
below.
PC
000H
Interrupt
Disable
WDT
Clear. After master reset,
WDT begins counting
T i m e r / E v e n t
Counter
Off
I n p u t / o u t p u t
Ports
Input mode
SP
Points to the top of the
stack
.
0 + # 7 ) , .
3 0 /# $ # .
Reset timing chart
Reset circuit
& " + # $ # .
) ' 2
# $ # .
1 $ . # + # $ # .
7 > 0 .0 / / ' #
) , - . # "
Reset configuration
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