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參數(shù)資料
| 型號： | HT46C63(100QFP) |
| 英文描述： | Microcontroller |
| 中文描述： | 微控制器 |
| 文件頁數(shù)： | 11/42頁 |
| 文件大小： | 362K |
| 代理商： | HT46C63(100QFP) |
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HT46R63/HT46C63
Rev. 1.00
11
September 9, 2002
Bank pointer
The bank pointer is used to assign the accessed RAM
bank. When the users want to access the RAM bank 0
a 0 should be loaded onto BP. When the BP is equal to
1 , the LCD
RAM will be accessed (use MP1/R1 indi-
rect addressing only). RAM locations before 40H in any
bank are overlapped.
Accumulator
The accumulator is closely related to ALU operations. It
is also mapped to location 05H of the data memory and
can carry out immediate data operations. The data
movement between two data memory locations must
pass through the accumulator.
Arithmetic and logic unit
ALU
This circuit performs 8-bit arithmetic and logic opera-
tions. The ALU provides the following functions:
Arithmetic operations (ADD, ADC, SUB, SBC, DAA)
Logic operations (AND, OR, XOR, CPL)
Rotation (RL, RR, RLC, RRC)
Increment and Decrement (INC, DEC)
Branch decision (SZ, SNZ, SIZ, SDZ ....)
The ALU not only saves the results of a data operation
but also changes the status register.
Status register
STATUS
This 8-bit register (0AH) contains the zero flag (Z), carry
flag (C), auxiliary carry flag (AC), overflow flag (OV),
power down flag (PD), and watchdog time-out flag (TO).
It also records the status information and controls the
operation sequence.
With the exception of the TO and PD flags, bits in the
status register can be altered by instructions like
most other registers. Any data written into the status
register will not change the TO or PD flag. In addition
operations related to the status register may give dif-
ferent results from those intended. The TO flag can
be affected only by system power-up, a WDT
time-out or executing the CLR WDT or HALT in-
struction. The PD flag can be affected only by exe-
cuting the
system power-up.
HALT
or
CLR WDT
instruction or a
The Z, OV, AC and C flags generally reflect the status of
the latest operations.
In addition, on entering the interrupt sequence or exe-
cuting the subroutine call, the status register will not be
pushed onto the stack automatically. If the contents of
the status are important and if the subroutine can cor-
rupt the status register, precautions must be taken to
save it properly.
Interrupt
The microcontroller provides two external interrupts, an
internal timer/event counter overflow interrupt, a time
base
time-out
interrupt,
end-of-conversion interrupt and a real time clock
time-out interrupt. The interrupt control registers
(INTC0: 0BH and INTC1: 1EH) contains the interrupt
control bits to set the enable or disable and the interrupt
request flags.
an
A/D
converter
Once an interrupt subroutine is serviced, all the other in-
terrupts will be blocked (by clearing EMI bit). This
schememaypreventanyfurtherinterruptnesting.Other
interrupt requests may happen during this interval but
only the interrupt request flags are recorded. If a certain
interrupt requires servicing within the service routine,
the programmer may set the EMI and the corresponding
bitofINTC0/INTC1toallowinterruptnesting.Ifthestack
is full, the interrupt request will not be acknowledged,
even if the related interrupt is enabled, until the SP is de-
creased. If immediate service is desired, the stack has
to be prevented from becoming full.
Labels
Bits
Function
C
0
C is set if an operation results in a carry during an addition operation or if a borrow does not take
place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through
carry instruction.
AC
1
AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from the
high nibble into the low nibble in subtraction; otherwise AC is cleared.
Z
2
Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is cleared.
OV
3
OV is set if the operation results in a carry into the highest-order bit but not a carry out of the high-
est-order bit, or vice versa; otherwise OV is cleared.
PD
4
PD is cleared by a system power-up or executing the CLR WDT instruction. PD is set by execut-
ing the HALT instruction.
TO
5
TO is cleared by system power-up or executing the CLR WDT or HALT instruction. TO is set
by a WDT time-out.
6, 7
Unused bit, read as 0
Status register
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