
HT36A4
Rev. 1.00
15
July 2, 2003
Afterachipreset,theseinput/outputlinesremainathigh
levels or floating (mask option). Each bit of these in-
put/output latches can be set or cleared by the SET [m].i
or CLR [m].i (m=12H) instruction.
Some instructions first input data and then follow the
output operations. For example, the SET [m].i, CLR
[m].i, CPL [m] and CPLA [m] instructions read the entire
port states into the CPU, execute the defined operations
(bit-operation), and then write the results back to the
latches or the accumulator.
Each line of port A has the capability to wake-up the de-
vice.
8 Channel Wavetable Synthesizer
wavetable Function Memory Mapping
Special Register for Wavetable Synthesizer
RAM
B7
B6
B5
B4
B3
B2
B1
B0
1DH
DA15
DA14
DA13
DA12
DA11
DA10
DA9
DA8
1EH
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
1FH
DAON
SELW
20H
VM
FR
CH2
CH1
CH0
21H
BL3
BL2
BL1
BL0
FR11
FR10
FR9
FR8
22H
FR7
FR6
FR5
FR4
FR3
FR2
FR1
FR0
23H
ST10
ST9
ST8
24H
ST7
ST6
ST5
ST4
ST3
ST2
ST1
ST0
25H
WBS
RE9
RE8
26H
RE7
RE6
RE5
RE4
RE3
RE2
RE1
RE0
27H
VR9
VR8
2AH
VR7
VR6
VR5
VR4
VR3
VR2
VR1
VR0
wavetable Function Register Table
Register
Name
Register Function
B7
B6
B5
B4
B3
B2
B1
B0
1DH
DAC high byte (no default value)
DA15 DA14
DA13
DA12
DA11
DA10
DA9
DA8
1EH
DAC low byte (no default value)
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
1FH
DAON=1: DAC ON
DAON=0: DAC OFF (default)
SELW=1: DAC data from wavetable
SELW=0: DAC data from MCU
DAON SELW
20H
Channel Number Selection
CH2
CH1
CH0
20H
Change Parameter Selection
VM
FR
21H
Block Number Selection
BL3
BL2
BL1
BL0
21H
Frequency Number Selection
FR11
FR10
FR9
FR8
22H
FR7
FR6
FR5
FR4
FR3
FR2
FR1
FR0
23H
Start Address Selection
ST10
ST9
ST8
24H
ST7
ST6
ST5
ST4
ST3
ST2
ST1
ST0
25H
Waveform Format Selection
WBS
25H
Repeat Number Selection
RE9
RE8
26H
RE7
RE6
RE5
RE4
RE3
RE2
RE1
RE0
27H
Volume Controller
VR9
VR8
2AH
VR7
VR6
VR5
VR4
VR3
VR2
VR1
VR0