參數(shù)資料
型號(hào): HT23C040H
英文描述: CMOS 512K?8-Bit High Speed Mask ROM
中文描述: 為512k的CMOS?8位高速掩模ROM
文件頁(yè)數(shù): 4/9頁(yè)
文件大?。?/td> 111K
代理商: HT23C040H
A.C. test condition
Output load: see figure right
Input rise and fall time: 10ns
Input pulse levels: 0.4V to 2.4V
Input and output timing reference levels:
0.8V and 2.0V (V
CC
=5V)
1.5V (V
CC
=3V)
Operation truth table
Mode
CE/CE
OE/OE
A0~A18
D0~D7
Read
H/L
H/L
Valid
Data Out
Deselect
H/L
L/H
X
High Z
Standby
L/H
X
X
High Z
Note: H=V
IH
, L=V
IL
, X=V
IH
or V
IL
Timing Diagrams
Propagation delay due to address (CE/CE and OE/OE are active)
Propagation delay due to chip and output enable (address valid)
HT23C040H
Rev. 1.00
4
August 15, 2002
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Output load circuit
Functional Description
The HT23C040H has two modes, namely data read
mode and standby mode, controlled by CE/CE and
OE/OE/NC inputs.
Standby mode
The HT23C040H offers lower current consumption,
controlled by the chip enable input (CE/CE). When a
low/high level is applied to the CE/CE input regardless
of the output enable (OE/OE/NC) states the chip will
enter the standby mode.
Data read mode
When both the chip enable (CE/CE) and the output
enable (OE/OE/NC) are active, the chip is in data read
mode. Otherwise, active CE/CE and inactive
OE/OE/NC result in deselect mode. The output will re-
main in Hi-Z state.
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