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參數(shù)資料
| 型號： | HT1670 |
| 廠商： | Holtek Semiconductor Inc. |
| 英文描述： | 128x32 LCD Controller for I/O MCU |
| 中文描述： | 128x32 LCD控制器的I / O控制器 |
| 文件頁數(shù)： | 12/19頁 |
| 文件大?。?/td> | 174K |
| 代理商： | HT1670 |
HT1670
Rev. 1.10
12
September 17, 2004
Bias Generator
The HT1670 bias voltage belongs to internal resistor
type. It provides two kinds of bias option named 1/6 bias
and 1/5 bias respectively. It also provides three kinds of
bias current option by programming to suitably drive an
LCD panel. The three kinds of bias current are large,
middle, and small, respectively. Usually, large panel
LCD can be excellently displayed by large bias current.
Relatively, it consumes large current when LCD ON
command is used. Small bias current provides low
power consumption during on condition when the LCD
is normally displayed. The following are the reference
value table.
When the bias current for LCD is more than Large Bias
Current setting. It is recommended to add external cir-
cuit to increase driving current.
Interfacing
Only six lines are required to interface with the HT1670.
The CS line is used to initialize the serial interface circuit
and to terminate the communication between the host
controller and the HT1670. If the CS pin is set to 1, the
data and command issued between the host controller
and the HT1670 are first disabled and then initialized.
Before issuing a mode command or mode switching, a
high level pulse is required to initialize the serial inter-
face of the HT1670. The DB0~DB3 are the 4-bit parallel
data input/output lines. Data to be read or written or
commands to be written have to pass through the
DB0~DB3 lines. The RD line is the READ clock input.
DataintheRAMareclockedoutonthefallingedgeofthe
RD signal, and the clocked out data will then appear on
the DB0~DB3 lines. It is recommended that the host
controller read correct data during the interval between
therisingedgeandthenextfallingedgeoftheRDsignal.
The WR line is the WRITE clock input. The data, ad-
dress, and command on the DB0~DB3 lines are all
clocked into the HT1670 on the rising edge of the WR
signal. There is an optional IRQ line to be used as an in-
terface between the host controller and the HT1670.
The IRQ pin can be selected as a timer output or a WDT
overflow flag output by the S/W setting. The host con-
troller can perform the time base or the WDT function by
connecting with the IRQ pin of the HT1670.
Bias
VLCD
Large Bias Current
Middle Bias Current
Small Bias Current
1/5
3V
165 A
70 A
30 A
5V
270 A
110 A
50 A
1/6
3V
140 A
55 A
25 A
5V
225 A
90 A
40 A
- ! !
- $
- 8
% 7
C
5
-
-
-
- ! !
;
' < - '
- $
- 8
;
% < - %
% 6
C
5
-
-
-
;
$ < - 6
;
8 < - 7
;
' < - '
;
% < - %
;
$ < - 6
;
8 < - 7
Internal Resistor Type Bias Generator Configurations
Note:
The voltage applied to VLCD pin must be lower than 7V
Adjust VR to fit LCD display
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