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參數(shù)資料
| 型號(hào)： | HT1623 |
| 廠商： | Holtek Semiconductor Inc. |
| 英文描述： | RAM Mapping 48x8 LCD Controller for I/O C |
| 中文描述： | 內(nèi)存映射48x8 LCD控制器的I /業(yè)主立案法團(tuán) |
| 文件頁數(shù)： | 9/18頁 |
| 文件大?。?/td> | 155K |
| 代理商： | HT1623 |
HT1623
9
April 21, 2000
Functional Description
Display memory
RAM structure
The static display RAM is organized into 96 4
bits and stores the display data. The contents of
the RAM are directly mapped to the contents of
the LCD driver. Data in the RAM can be
a c c e s s e d b y t h e R E A D , W R I T E a n d
READ-MODIFY-WRITE commands. The fol-
lowing is a mapping from the RAM to the LCD
patterns.
Time base and watchdog timer
WDT
The time base generator and WDT share the
samedivided(/256)counter.TIMERDIS/EN/CLR,
WDT DIS/EN/CLR and IRQ EN/DIS are inde-
pendent from each other. Once the WDT
time-out occurs, the IRQ pin will remain at
logic low level until the CLR WDT or the IRQ
DIScommandisissued.
! ! (
! ! (
$ $ % *
3
4 $
4 $
4 $
5
! ! ( ' * * $ $ %
4 $
4 $ : : : : 4 $
3
5
RAM mapping
$
$
/
9
$
, " 7 $ " 0 ( '
/
/
% & ' $ * '
$% & ' (
$
/
Timer and WDT configurations
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