VCC +5V power supply pin. GND Ground P0" />
參數(shù)資料
型號: HSP45102SC-40Z
廠商: Intersil
文件頁數(shù): 3/9頁
文件大?。?/td> 0K
描述: IC OSC NCO 40MHZ 28-SOIC
標準包裝: 26
類型: 數(shù)控振蕩器(NCO)
頻率: 40MHz
電源電壓: 4.75 V ~ 5.25 V
電流 - 電源: 99mA
工作溫度: 0°C ~ 70°C
封裝/外殼: 28-SOIC(0.295",7.50mm 寬)
包裝: 管件
供應(yīng)商設(shè)備封裝: 28-SOIC W
安裝類型: 表面貼裝
3
FN2810.9
April 25, 2007
Pin Description
NAME
TYPE
DESCRIPTION
VCC
+5V power supply pin.
GND
Ground
P0-1
I
Phase modulation inputs (become active after a pipeline delay of four clocks). A phase shift of 0°, 90°,
180°, or 270° can be selected as shown in Table 1.
CLK
I
NCO clock. (CMOS level)
SCLK
I
This pin clocks the frequency control shift register.
SEL_L/M
I
A high on this input selects the least significant 32 bits of the 64-bit frequency register as the input to
the phase accumulator; a low selects the most significant 32 bits.
SFTEN
I
The active low input enables the shifting of the frequency register.
MSB/LSB
I
This input selects the shift direction of the frequency register. A low on this input shifts in the data LSB
first; a high shifts in the data MSB first.
ENPHAC
I
This pin, when low, enables the clocking of the Phase Accumulator. This input has a pipeline delay of
four clocks.
SD
I
Data on this pin is shifted into the frequency register by the rising edge of SCLK when SFTEN is low.
TXFR
I
This active low input is clocked onto the chip by CLK and becomes active after a pipeline delay of four
clocks. When low, the frequency control word selected by SEL_L/M is transferred from the frequency
register to the phase accumulator’s input register.
LOAD
I
This input becomes active after a pipeline delay of five clocks. When low, the feedback in the phase
accumulator is zeroed.
OUT0-11
O
Output data. OUT0 is LSB. Unsigned.
All inputs are TTL level, with the exception of CLK.
Overline designates active low signals.
HSP45102
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