參數(shù)資料
型號: HPFC-5100D
英文描述: Tachyon TL Mass Storage Fibre Channel IC Rev 3.0
中文描述: 商標法的Tachyon光纖通道海量存儲集成電路活3.0
文件頁數(shù): 4/4頁
文件大小: 166K
代理商: HPFC-5100D
Command & Data Management
Context Switching
16-entry on-chip cache for low latency context save and restore, as
well as extensive pipelining techniques
Through the use of local memory option
Yes, independent inbound and outbound FIFOs with automatic
hardware management of buffer-to-buffer credit
Yes, with support for local and extended Scatter/Gather lists for
unlimited “chaining” of Length/Address pairs
6 to optimize concurrency and PCI utilization
All data paths at byte level
Reduced PCI Control Overhead
Full Duplex Support
Full Scatter/Gather List Support
DMA Channels
Parity Protection
Optional External Memory Interface
Interface
Memory Supported
32-bit @ 33 MHz for 132 MBytes/second
128 K or 256 K bytes of synchronous static RAM for optional low
latency control access
Flash and ROM support for Boot BIOS and Subsystem Vendor ID
No
Parity Protection
Test & Debug
JTAG
Full Internal Scan
Hardware Debug Capability
Link Status Indicators
User Definable Signal Pins
Packaging
Package
Yes
Yes, IEEE Standard 1149.1 Boundary Scan
Yes
Yes
Link up/down, low-speed serial interface or custom
272-pin Enhanced Plastic Ball Grid Array (PBGA+)
Tachyon TL Specifications
, continued
www.semiconductor.agilent.com
Data subject to change.
Copyright 1999 Agilent Technologies, Inc.
5968-5303E (11/99)
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