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| 型號： | HMS87C1304A |
| 廠商： | Hynix Semiconductor Inc. |
| 英文描述： | CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER |
| 中文描述： | CMOS單芯片8位微控制器 |
| 文件頁數(shù)： | 35/70頁 |
| 文件大?。?/td> | 977K |
| 代理商： | HMS87C1304A |
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HYUNDAI MicroElectronics
HMS87C1304A/HMS87C1302A
Jan. 2001
Preliminary
35
11. Basic Interval Timer
The HMS87C1304A and HMS87C1302A has one 8-bit
Basic Interval Timer that is free-run, can not stop. Block
diagram is shown in Figure 11-1 .The 8-bit Basic interval
timer register (BITR) is increased every internal count
pulse which is divided by prescaler. Since prescaler has di-
vided ratio by 8 to 1024, the count rate is 1/8 to 1/1024 of
the oscillator frequency. As the count overflows from FF
H
to 00
H
, this overflow causes to generate the Basic interval
timer interrupt. The BITF is interrupt request flag of Basic
interval timer.
When write “1” to bit BTCL of CKCTLR, BITR register is
cleared to “0” and restart to count-up. The bit BTCL be-
comes “0” after one machine cycle by hardware.
If the STOP instruction executed after writing “1” to bit
WAKEUP of CKCTLR, it goes into the wake-up timer
mode. In this mode, all of the block is halted except the os-
cillator, prescaler (only fxin
÷
2048) and Timer0.
If the STOP instruction executed after writing “1” to bit
ed watchdog timer mode. In this mode, all of the block is
halted except the internal RC oscillator, Basic Interval
Timer and Watchdog Timer. More detail informations are
explained in Power Saving Function. The bit WDTON de-
cides Watchdog Timer or the normal 7-bit timer
Note:
All control bits of Basic interval timer are in CKCTLR
register which is located at same address of BITR
(address EC
H
). Address EC
H
is read as BITR, writ-
ten to CKCTLR. Therefore, the CKCTLR can not be
accessed by bit manipulation instruction..
Figure 11-1 Block Diagram of Basic Interval Timer
Figure 11-2 CKCTLR: Clock Control Register
÷
8
÷
16
÷
32
÷
64
÷
128
÷
256
÷
512
÷
1024
0
1
MUX
8
3
fxin
BITR (8BIT)
BITIF
BTS[2:0]
Internal RC OSC
Basic Interval Timer
Interrupt
BTCL
Clear
To Watchdog Timer
STOP
WAKEUP
RCWDT
Clock Control Register
CKCTLR
ADDRESS : ECH
RESET VALUE : -0010111
Bit Manipulation Not Available
-
WAKEUP
RCWDT
WDTON
BTCL
BTS2
BTS1
BTS0
Basic Interval Timer Clock Selection
000 : fxin
÷
8
001 : fxin
÷
16
010 : fxin
÷
32
011 : fxin
÷
64
100 : fxin
÷
128
101 : fxin
÷
256
110 : fxin
÷
512
111 : fxin
÷
1024
Symbol
Function Description
WAKEUP
1 : Enables Wake-up Timer
0 : Disables Wake-up Timer
RCWDT
1 : Enables Internal RC Watchdog Timer
0 : Disables Internal RC Watchdog Time
WDTON
1 : Enables Watchdog Timer
0 : Operates as a 7-bit Timer
BTCL
1 : BITR is cleared and BTCL becomes “0” automatically
after one machine cycle, and BITR continue to count-up
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