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參數(shù)資料
| 型號： | HMS77C1001A |
| 廠商： | Hynix Semiconductor Inc. |
| 元件分類： | 數(shù)學(xué)處理器 |
| 英文描述： | 8-BIT SINGLE-CHIP MICROCONTROLLERS |
| 中文描述： | 8位單晶片微控制器 |
| 文件頁數(shù)： | 45/45頁 |
| 文件大?。?/td> | 549K |
| 代理商： | HMS77C1001A |
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HMS77C1000A/HMS77C1001A
42
Oct. 2001 Ver. 2.0
18. POWER FAIL DETECTION PROCESSOR
HMS77C100XA has an on-chip power fail detection cir-
cuitry to immunize against power noise.
If V
DD
falls below a level for longer 100ns, the power fail
detection processor may reset MCU and preserve the de-
vice from the malfunction due to Power Noise.
The bit6(PFDEN) of OPTION register activates the PFD
Circuit, and bit7(LOWopt) lowers the detection level of
the Power Noise. The normal detection level is typically
2.7V and the lowered detection level is typically 1.8V. Fig-
ure 18-2 shows a Power Fail Detection Situations where
the detection level is selected by LOWOPT Bit.
Note:
The PFD circuit is not implemented on the in circuit
emulator, user can not experiment with it. There
fore, after final development user program, this
function may be experimented on OTP
FIGURE 18-1 POWER FAIL DETECTION PROCESSOR
LOWOPT PFDEN
T0CS
T0SE
PSA
PS2
PS1
PS0
bit7
6
bit0
5
4
3
2
1
bit 7
LOWOPT
: Power-fail detection level select bit.
1 = Lowered detection level (typ. 1.8V @ 5V)
0 = Normal detection level (typ. 2.7V @ 5V)
bit 6
PFDEN
: Power-fail detection enable bit
1 = Enable power-fail detection
0 = Disable power-fail detection
OPTION
Register
FIGURE 18-2 POWER FAIL DETECTION SITUATIONS
Internal
RESET
V
DD
V
DR
=2.7V
T
NVDD
≥
100nS
PFDEN = 1
LOWOPT = 0
PFDR
T
IRT
Internal
RESET
V
DD
V
DR
=1.8V
T
NVDD
≥
100nS
PFDR
T
IRT
Internal
RESET
V
DD
V
DR
=2.7 or 1.8V
PFDR
T
IRT
POR
PFDEN = 1
LOWOPT = 0/1
V
DD
≤
V
DR
PFDEN = 1
LOWOPT = 1
When V
DD
falls below approximately 1.5V level, Power-On Reset may occur.
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