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參數(shù)資料
| 型號： | HMP817xEVAL1 |
| 廠商： | Intersil Corporation |
| 英文描述： | GIGATRUE 550 CAT6 PATCH 1 FT, SNAGLESS, WHITE |
| 中文描述： | NTSC / PAL視頻編碼器 |
| 文件頁數(shù)： | 26/33頁 |
| 文件大?。?/td> | 232K |
| 代理商： | HMP817XEVAL1 |
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26
Video Level Error
Internal Voltage Reference
(Note 5)
VREF Unconnected, RSET = 133
VREF = 1.230V (Figure 27), RSET = 140
-
-
±
10
±
10
%
External Voltage Reference
-
-
%
DAC to DAC Matching
-
-
5
%
VREF Output Voltage
Pin not connected, using internal reference
1.13
1.19
1.32
V
VREF Output Current
-50
-
50
μ
A
VREF Input Voltage
Pin connected to external reference shown in
Figure 27.
1.11
1.23
1.36
V
VREF Input Current
-500
-
500
μ
A
AC PARAMETERS, ANALOG OUTPUTS
Differential Gain Error
Using analog output filter shown in Figure 28A.
-
1
-
%
Differential Phase Error
-
1
-
Degree
SNR (Weighted)
-
70
-
dB
Hue Accuracy
-
2
-
Degree
Color Saturation Accuracy
-
2
-
%
Luminance Nonlinearity
-
1
-
%
Residual Subcarrier
-
-60
-
dB
SCH Phase
SCH Phase Reset enabled
-
±
1.5
-
Degree
Analog Output Skew, t
ASK
Analog Output Delay, t
AD
DAC-DAC Crosstalk
-
-
3
ns
-
-
12
ns
-
-60
-
dB
Glitch Energy
Using analog output filter shown in Figure 28A.
Includes clock and data feedthrough
-
35
-
pV-s
AC PARAMETERS, DIGITAL INPUTS AND OUTPUTS EXCEPT SCL AND SDA
Setup Time, t
S
Hold Time, t
H
CLK2 to Output Delay, t
D
CLK2 Frequency
Note 6.
8
-
-
ns
0
-
-
ns
3
-
15
ns
-
-
30.0
MHz
CLK2 High Time, CLK2
H
CLK2 Low Time, CLK2
L
RESET* Pulse Width Low, t
RES
13.6
-
20.3
ns
13.6
-
20.3
ns
4
-
-
CLK
Cycles
AC PARAMETERS, SCL AND SDA (I
2
C INTERFACE)
All AC parameters meet the fast-mode I
2
C Bus Interface specification.
POWER SUPPLY CHARACTERISTICS
DAC PSRR at DC
Note 7
-
64
-
dB
Power Supply Range, V
AA
Normal Supply Current, I
AA
Power-Down Supply Current, I
AA
Power Dissipation
4.75
5.0
5.25
V
-
-
260
mA
Note 8
-
-
750
μ
A
-
1100
1300
mW
NOTES:
5. Output level is dependent on the voltage on VREF, the value of RSET, and the load.
6. Test performed with C
L
= 40pF, I
O
=
±
2mA, V
IH
= 3.0V, V
IL
= 0.0V. Input reference level is 2.0V for all inputs.
7. The supply voltage rejection is the relative variation of the full-scale output driving a 37.5
load for a
±
5% supply variation:
PSRR = 20 x log (
V
AA
/
V
OUT
).
8. If using an external voltage reference, it is not powered down. The internal voltage reference is powered down.
Electrical Specifications
V
AA
= +5V
±
5%, RSET = 133
, VREF Unconnected, T
A
= 25
o
C, Unless Otherwise Specified
(Continued)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNITS
HMP8170, HMP8171, HMP8172, HMP8173
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HMP8171CN | NTSC/PAL Video Encoder |
| HMP8172 | NTSC/PAL Video Encoder |
| HMP8172CN | NTSC/PAL Video Encoder |
| HMP8170 | NTSC/PAL Video Encoder |
| HMP8170CN | NTSC/PAL Video Encoder |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HMP8190 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:NTSC/PAL Video Encoder |
| HMP8190CN | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:NTSC/PAL Video Encoder |
| HMP8190EVAL1 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:NTSC/PAL Video Encoder |
| HMP8191 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:NTSC/PAL Video Encoder |
| HMP8191CN | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:NTSC/PAL Video Encoder |
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