參數(shù)資料
型號(hào): HMMC-3002
英文描述: DC-16 GHz GaAs HBT MMIC Divide-by-2 Prescaler(DC-16 GHz 砷化鎵HBT單片微波集成電路除2定標(biāo)器)
中文描述: 的DC - 16 GHz的GaAs HBT的單片分頻2分頻器(直流- 16 GHz的砷化鎵HBT的單片微波集成電路除2定標(biāo)器)
文件頁(yè)數(shù): 4/8頁(yè)
文件大?。?/td> 266K
代理商: HMMC-3002
4
Applications
The HMMC-3002 is designed for
use in high frequency communi-
cations, microwave instrumenta-
tion and EW radar systems where
low phase-noise PLL control
circuitry or broad-band frequency
translation is required.
Operation
The device is designed to operate
when driven with either a single-
ended or differential sinusoidal
input signal over a 200 MHz to
16 GHz bandwidth. Below
200 MHz the prescaler input is
“slew-rate” limited requiring fast
rising and falling edge speeds to
properly divide. The device will
operate at frequencies down to
DC when driven with a square-
wave. AC coupling at the RFin
pad is recommended for most
applications.
The device can be operated from
either a single positive or single
negative supply. For positive
supply operation V
CC
is nominally
biased at any voltage in the +4.5
to +6.5 volt range with V
EE
(or
V
EE
& V
PwrSel
) grounded. For
negative bias operation V
CC
is
typically grounded and a negative
voltage between -4.5 to -6.5 volts
is applied to Vp
EE
(or V
EE
&
V
PwrSel
).
Several features are designed into
this prescaler:
1) Dual-Output Power
Feature
Bonding both V
EE
and V
PwrSel
pads
to either ground (positive bias
mode) or the negative supply
(negative bias mode), will deliver
~6.0 dBm [0.99 V
p-p
] at the RF
output port while drawing
~80 mA supply current. Eliminat-
ing the V
PwrSel
connection results
in reduced output power and
voltage swing, 0 dBm [0.5 V
p-p
]
but at a reduced current draw of
~60 mA resulting in less overall
power dissipation.
(NOTE: V
EE
must ALWAYS be bonded and
V
PwrSel
must NEVER be biased to
any potential other than V
EE
or
open-circuited.)
2) V
Logic
ECL Contact Pad
Under normal conditions no
connection or external bias is
required to this pad and it is self-
biased to the on-chip ECL logic
threshold voltage (V
CC
-1.35 V).
The user can provide an external
bias to this pad (1.5 to 1.2 volts
less than V
CC
) to force the
prescaler to operate at a system
generated logic threshold
voltage.
3) Input Disable Feature
By applying an external bias to
this contact pad (more positive
than V
CC
- 1.35 V),the input
preamplifier stage is locked into
either logic
“high”
or logic
“l(fā)ow”
preventing frequency division and
any self-oscillation frequency
which may be present.
4) Prescaler Power-Down
By applying an external bias to
this contact pad (more positive
than V
EE
+ 3.2V), the supply
current can be reduced to ~5 mA
also preventing frequency divi-
sion and any self-oscillation fre-
quency which may be present
while decreasing the power
dissipation to ~zero.
5) Input DC Offset
Another method used to prevent
false triggers or self-oscillation
conditions is to apply a 20 to
100 mV DC offset voltage be-
tween the RFin and RFin ports.
This prevents noise or spurious
low level signals from triggering
the divider.
Optional DC Operating Values/Logic Levels
(T
A
= 25
°
C)
Function
Symbol
Conditions
Min.
Typical
( volts/mA)
V
CC
- 1.35
V
Logic
Max.
( volts/mA)
V
CC
- 1.5
V
Logic
+ 0.25
V
EE
( volts/mA)
V
CC
- 1.2
V
CC
V
Logic
- 0.25
Logic Threshold
[1]
V
Logic
V
Disable(High)
[Disable]
V
Disable(Low)
[Enable]
Input Disable
I
Disable
V
D
> V
EE
+ 3
V
D
< V
EE
+ 3
(V
Disable
- V
EE
- 3) / 500
0
V
EE
+ 3.2
V
PwrDwn(High)
[Power-Down]
V
PwrDwn(Low)
[Power-Up]
V
EE
+ 3.9
V
EE
V
CC
Prescaler
Power-Down
V
EE
+ 2.7
I
PwrDwn
V
P
> V
EE
+ 2.7
V
P
< V
EE
+ 2.7
(V
PwrDwn
-V
EE
- 3) / 500
0
Note:
1. Acceptable voltage range when applied from external source.
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