參數(shù)資料
型號: HMD4M36M9EAG-5
廠商: Hanbit Electronics Co.,Ltd.
英文描述: 16Mbyte(4Mx36) 72-pin SIMM, EDO with Parity Mode, 2K/4K Ref. 5V
中文描述: 16Mbyte(4Mx36)72引腳平價模式,2K/4K參考上海藥物研究所,江戶。 5V的
文件頁數(shù): 4/7頁
文件大?。?/td> 67K
代理商: HMD4M36M9EAG-5
HANBit HMD4M36M9EG, HMD4M36M9EA
URL:
www.hbe.co.kr
HANBit Electronics Co.,Ltd.
REV. 1.0. (August. 2002)
- 4 -
I
CC6
: /CAS-Before-/RAS Refresh Current * (/RAS and /CAS cycling @t
RC
=min )
I
IL
: Input Leakage Current (Any input 0V
V
IN
6.5V, all other pins not under test = 0V)
I
OL
: Output Leakage Current (Data out is disabled, 0V
V
OUT
5.5V
V
OH
: Output High Voltage Level (I
OH
= -5mA )
V
OL
: Output Low Voltage Level (I
OL
= 4.2mA )
*
NOTE
: I
CC1
, I
CC3
, I
CC4
and I
CC6
are dependent on output loading and cycle rates. Specified values are obtained with the
output open. I
CC
is specified as an average current. In I
CC1
and I
CC3
, address cad be changed maximum once
while /RAS=V
IL
. In I
CC4
, address can be changed maximum once within one page mode cycle.
CAPACITANCE
( T
A
=25
o
C, Vcc = 5V, f = 1Mz )
DESCRIPTION
SYMBOL
MIN
MAX
UNITS
Input Capacitance (A0-A10)
C
IN1
-
65
pF
Input Capacitance (/W)
C
IN2
-
80
pF
Input Capacitance (/RAS0)
C
IN3
-
50
pF
Input Capacitance (/CAS0-/CAS3)
C
IN4
-
40
pF
Input/Output Capacitance (DQ0-31)
C
DQ1
-
20
pF
AC CHARACTERISTICS
( 0
o
C
T
A
70oC , Vcc = 5V
±
10%, See notes 1,2.)
-5
-6
STANDARD OPERATION
SYMBOL
MIN
MAX
MIN
MAX
UNIT
Random read or write cycle time
t
RC
90
110
ns
Access time from RAS
t
RAC
50
60
ns
Access time from CAS
t
CAC
13
15
ns
Access time from column address
t
AA
25
30
ns
CAS to output in Low-Z
t
CLZ
3
3
ns
Output buffer turn-off delay
t
OFF
3
13
3
15
ns
Transition time (rise and fall)
t
T
2
50
2
50
ns
/RAS precharge time
t
RP
30
40
ns
/RAS pulse width
t
RAS
50
10K
60
10K
ns
/RAS hold time
t
RSH
13
15
ns
/CAS hold time
t
CSH
38
45
ns
/CAS pulse width
t
CAS
8
10K
10
10K
ns
/RAS to /CAS delay time
t
RCD
20
37
20
45
ns
/RAS to column address delay time
t
RAD
15
25
15
30
ns
/CAS to /RAS precharge time
t
CRP
5
5
ns
Row address set-up time
t
ASR
0
0
ns
Row address hold time
t
RAH
10
10
ns
Column address set-up time
t
ASC
0
0
ns
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