參數(shù)資料
型號(hào): HMD4M36M9AG-5
廠商: Hanbit Electronics Co.,Ltd.
英文描述: 16Mbyte(4Mx36) Fast Page with Parity Mode, 2K/4K Refresh
中文描述: 16Mbyte(4Mx36)快速頁模式與校驗(yàn),2K/4K刷新
文件頁數(shù): 4/7頁
文件大小: 71K
代理商: HMD4M36M9AG-5
HANBiT HMD4M36M9G, HMD4M36M9AG
URL:www.hbe.co.kr
- 4 - HANBit Electronics Co.,Ltd.
REV.1.0 (August.2002)
I
CC5
: Standby Current (/RAS=/CAS=Vcc-0.2V )
I
CC6
: /CAS-Before-/RAS Refresh Current * (/RAS and /CAS cycling @t
RC
=min )
I
IL
: Input Leakage Current (Any input 0V
V
IN
6.5V, all other pins not under test = 0V)
I
OL
: Output Leakage Current (Data out is disabled, 0V
V
OUT
5.5V
V
OH
: Output High Voltage Level (I
OH
= -5mA )
V
OL
: Output Low Voltage Level (I
OL
= 4.2mA )
* NOTE
: I
CC1
, I
CC3
, I
CC4
and I
CC6
are dependent on output loading and cycle rates. Specified values are obtained with the
output open. I
CC
is specified as an average current. In I
CC1
and I
CC3
, address cad be changed maximum once while
/RAS=V
IL
. In I
CC4
, address can be changed maximum once within one page mode cycle.
CAPACITANCE
( T
A
=25
o
C, Vcc = 5V, f = 1Mz )
DESCRIPTION
SYMBOL
MIN
MAX
UNITS
Input Capacitance (A0-A10)
C
IN1
-
70
pF
Input Capacitance (/WE)
C
IN2
-
80
pF
Input Capacitance (/RAS0, /RAS2)
C
IN3
-
80
pF
Input Capacitance (/CAS0-/CAS3)
C
IN4
-
40
pF
Input / Output Capacitance (DQ0-35)
C
DQ
-
17
pF
AC CHARACTERISTICS
( 0
o
C
T
A
70oC , Vcc = 5V
±
10%, See notes 1,2.)
-5
-6
STANDARD OPERATION
SYMBOL
MIN
MAX
MIN
MAX
UNIT
Random read or write cycle time
t
RC
90
110
ns
Access time from /RAS
t
RAC
50
60
ns
Access time from /CAS
t
CAC
13
15
ns
Access time from column address
t
AA
25
30
ns
/CAS to output in Low-Z
t
CLZ
0
0
ns
Output buffer turn-off delay
t
OFF
0
13
0
15
ns
Transition time (rise and fall)
t
T
3
50
3
50
ns
/RAS precharge time
t
RP
30
40
ns
/RAS pulse width
t
RAS
50
10K
60
10K
ns
/RAS hold time
t
RSH
13
15
ns
/CAS hold time
t
CSH
50
60
ns
/CAS pulse width
t
CAS
13
10K
15
10K
ns
/RAS to /CAS delay time
t
RCD
20
37
20
45
ns
/RAS to column address delay time
t
RAD
15
25
15
30
ns
/CAS to /RAS precharge time
t
CRP
5
5
ns
Row address set-up time
t
ASR
0
0
ns
Row address hold time
t
RAH
10
10
ns
Column address set-up time
t
ASC
0
0
ns
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