參數(shù)資料
型號(hào): HMD2M64B2-10
廠商: Hanbit Electronics Co.,Ltd.
英文描述: Synchronous DRAM Module 16Mbyte (2Mx64-Bit), SO-DIMM, 4Banks, 4K Ref., 3.3V
中文描述: 同步DRAM模塊16Mbyte(2Mx64位),SO - DIMM插槽,4Banks,4K的參考。,3.3
文件頁(yè)數(shù): 7/10頁(yè)
文件大?。?/td> 87K
代理商: HMD2M64B2-10
HANBit HSD2M64B2
URL:www.hbe.co.kr HANBit Electronics Co.,Ltd.
REV.1.0 (August.2002)
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
VERSION
PARAMETER
SYMBOL
-8
-10
UNIT
NOTE
Row active to row active delay
t
RRD
(min)
2
2
ns
1
RAS to CAS delay
t
RP
(min)
3
2
ns
1
Row precharge time
t
RP
(min)
3
2
ns
1
t
RAS
(min)
6
5
ns
1
Row active time
t
RAS
(max)
100
ns
Row cycle time
tRC
(min)
9
7
ns
1
Last data in to row precharge
t
RDL
(min)
2
CLK
2.5
Last data in to new col. address delay
t
CDL
(min)
1
CLK
2
Last data in to burst stop
t
BDL
(min)
1
CLK
2
Col. address to col. address delay
t
CCD
(min)
1
CLK
3
CAS latency=3
2
Number of valid output data
CAS latency=2
1
ea
4
Notes :
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and
then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
.
+3.3V
1200
870
50pF*
D
OUT
V
tt
=1.4V
50
50pF
D
OUT
Z0=50
V
OH
(DC) = 2.4V, I
OH
= -2mA
V
OL
(DC) = 0.4V, I
OL
= 2mA
(Fig. 1) DC output load circuit
(Fig. 2) AC output load circuit
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