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參數(shù)資料
| 型號： | HMD2M32M4EG-6 |
| 廠商： | Hanbit Electronics Co.,Ltd. |
| 英文描述： | 8Mbyte(2Mx32) EDO Mode, 1K Refresh 72Pin SIMM, 5V Design |
| 中文描述： | 8Mbyte（2Mx32）EDO公司模式，每1000刷新72Pin上海藥物研究所，5V的設(shè)計 |
| 文件頁數(shù)： | 5/7頁 |
| 文件大?。?/td> | 145K |
| 代理商： | HMD2M32M4EG-6 |
HANBit HMD2M32M4E/4EG
URL:www.hbe.co.kr HANBit Electronics Co.,Ltd.
REV.1.0 (August.2002)
Column address set-up time
t
ASC
0
0
ns
Column address hold time
t
CAH
8
10
ns
Column Address to /RAS lead time
t
RAL
25
30
ns
Read command set-up time
t
RCS
0
0
ns
Read command hold referenced to /CAS
t
RCH
0
0
ns
Read command hold referenced to /RAS
t
RRH
0
0
ns
Write command hold time
t
WCH
10
10
ns
Write command pulse width
t
WP
10
10
ns
Write command to /RAS lead time
t
RWL
13
15
ns
Write command to /CAS lead time
t
CWL
13
15
ns
Data-in set-up time
t
DS
0
0
ns
Data-in hold time
t
DH
8
10
ns
Refresh period (1K Ref. Normal)
t
REF
16
16
ms
Write command set-up time
t
WCS
0
0
ns
/CAS setup time (C-B-R refresh)
t
CSR
5
5
ns
/CAS hold time (C-B-R refresh)
t
CHR
10
10
ns
/RAS precharge to /CAS hold time
t
RPC
5
5
ns
Access time from /CAS precharge
t
CPA
30
35
ns
/CAS precharge time (Fast page)
t
CP
8
10
ns
/RAS pulse width (Fast page )
t
RASP
50
200K
60
200K
ns
/W to /RAS precharge time (C-B-R refresh)
t
WRP
10
10
ns
/W to /RAS hold time (C-B-R refresh)
t
WRH
10
10
ns
NOTES
1.
An initial pause of 200
μ
s is required after power-up followed by any 8 /RAS-only or /CAS-before-/RAS refresh cycles
before proper device operation is achieved.
2.
V
IH (min)
and V
IL (max)
are reference levels for measuring timing of input signals. Transition times are measured between
V
IH(min)
and V
IL(max)
and are assumed to be 5ns for all inputs.
3.
Measured with a load equivalent to 2TTL loads and 100pF
4.
Operation within the t
RCD(max)
limit insures that t
RAC(max)
can be met. t
RCD(max)
is specified as a reference point only. If t
RCD
is greater than the specified t
RCD(max)
limit, then access time is controlled exclusively by t
CAC
.
5.
Assumes that t
RCD
≥
t
RCD(max)
6. t
AR
, t
WCR
, t
DHR
are referenced to t
RAD(max)
7.This parameter defines the time at which the output achieves the open circuit condition and is not referenced to V
OH
or V
OL
.
8. t
WCS
, t
RWD
, t
CWD
and t
AWD
are non restrictive operating parameter.
They are included in the data sheet as electrical characteristic only. If t
WCS
≥
tWCS(min)
the cycle is an early write
cycle and the data out pin will remain high impedance for the duration of the cycle.
9. Either t
RCH
or t
RRH
must be satisfied for a read cycle.
10. These parameters are referenced to the /CAS leading edge in early write cycles and to the /W leading edge in read -
write cycles.
11. Operation within the t
RAD(max)
limit insures that t
RAC(max)
can be met. t
RAD(max)
is specified as a reference
point only. If t
RAD
is greater than the specified t
RAD(max)
limit. then access time is controlled by t
AA
.
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相關(guān)代理商/技術(shù)參數(shù) |
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| HMD2M32M4EG-7 | 制造商:HANBIT 制造商全稱:Hanbit Electronics Co.,Ltd 功能描述:8Mbyte(2Mx32) EDO Mode, 1K Refresh 72Pin SIMM, 5V Design |
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| HMD2M64B2-F10 | 制造商:HANBIT 制造商全稱:Hanbit Electronics Co.,Ltd 功能描述:Synchronous DRAM Module 16Mbyte (2Mx64-Bit), SO-DIMM, 4Banks, 4K Ref., 3.3V |
| HMD2M64B2-F8 | 制造商:HANBIT 制造商全稱:Hanbit Electronics Co.,Ltd 功能描述:Synchronous DRAM Module 16Mbyte (2Mx64-Bit), SO-DIMM, 4Banks, 4K Ref., 3.3V |
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