參數(shù)資料
型號(hào)： HMD1M32M2GL-5
廠商： Hanbit Electronics Co.,Ltd.
英文描述： 4Mbyte(1Mx32) Fast Page Mode, 1K Refresh, 72Pin SIMM, 5V Design
中文描述： 4Mbyte（1Mx32）快速頁面模式，每1000刷新，72Pin上海藥物研究所，5V的設(shè)計(jì)
文件頁數(shù)： 5/7頁
文件大?。?/td> 201K
代理商： HMD1M32M2GL-5
HANBit HMD1M32M2GL
URL:www.hbe.co.kr
HANBit Electronics Co., Ltd.
REV.1.0 (August.2002)
tRRH
Read Command Hold Time to /RAS
0
0
ns
8
tWCH
Write Command Hold Time
10
10
ns
tWP
Write Command Pulse Width
10
10
ns
tRWL
Write Command to /RAS Lead Time
13
15
ns
tCWL
Write Command to /CAS Lead Time
13
15
ns
tDS
Data-in Setup Time
0
0
ns
9
tDH
Data-in Hold Time
10
10
ns
9
t
REF
Refresh Period (1024 Cycle)
16
16
ms
twcs
Write Command Setup Time
0
0
ms
7
tCWD
/CAS to /WE delay time
36
40
ms
7,13
tRWD
/RAS to /WE delay time
73
85
ns
7
tAWD
Column Address to /WE delay time
48
55
ns
7
tCPWD
/CAS precharge to /WE delay time
53
60
ns
7
tCSR
/CAS Setup Time
(/CAS-before-/RAS Refresh Cycle)
5
5
ns
15
tCHR
/CAS Hold Time
(/CAS-before-/RAS Refresh Cycle)
10
10
ns
16
tRPC
/RAS Precharge to /CAS Hold Time
5
5
ns
tCPA
Access Time from /CAS Precharge
30
35
ns
3
tPC
Fast Page Mode Cycle Time
35
40
ns
tCP
Fast Page Mode /RAS Precharge Time
10
10
ns
12
tRASP
Fast Page Mode /CAS Pulse Time
50
200K
60
200K
ns
tRHCP
/RAS Hold Time time from /CAS
Precharge
30
35
ns
tOEA
/OE Access Time
13
15
ns
3
tOED
/OE to data delay
13
15
ns
tOEZ
Output buffer turn off delay time from /OE
0
13
0
15
ns
tOEH
/OE command hold time
13
15
ns
tRASS
/RAS Pulse Width(CBR self refresh)
100
100
us
t
PRS
/RAS Precharge Time(CBR self refresh)
90
110
ns
tCHS
/CAS Hold Time(CBR self refresh)
Note:
1. An initial pause of 200us is required after power-up followed by any 8 /RAS-only refresh or /CAS-before-/RAS
refresh cycles before proper device operation is achieved.
2. Input voltage levels are V
/
V
V
(min) and V
IL
(max) are reference levels for measuring timing of input signals.
Also, transition times are measured between
V
and V
are assumed to be 5ns for all inputs.
3. Measured with a load circuit equivalent to 2TTL loads and 100pF.
4. Operation with the
t
(max) limit insures that
t
(max) can be met,
t
(max) is specified as a reference point only,
if
t
RCD
is greater than the specified
t
RCD
(max) limit, then access time is controlled exclusively by
t
CAC
.
5. Assumes that
t
<=
t
(max).
6. This parameter defines the time at which the output achieves the open circuit condition and is not referenced to V
OH
/
V
OL .
7. T
T
RWD,
T
CWD,
T
CPWD
are non restrictive operating parameter. They are included in the data sheet as electrical
characteristics
only. If
t
wcs
>=
t
wcs
(min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance)
throughout
-50
-50
ns
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