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參數(shù)資料
| 型號： | HMD16M72D9A-F13 |
| 廠商： | Hanbit Electronics Co.,Ltd. |
| 英文描述： | Synchronous DRAM Module 128Mbyte (8Mx72bit),DIMM with ECC based on 16Mx8, 4Banks, 4K Ref., 3.3V |
| 中文描述： | 同步DRAM模塊128Mbyte（8Mx72bit），帶ECC內(nèi)存的基礎(chǔ)上16Mx8，4Banks，4K的參考。，3.3 |
| 文件頁數(shù)： | 8/9頁 |
| 文件大?。?/td> | 95K |
| 代理商： | HMD16M72D9A-F13 |
HANBit HSD16M72D9A
URL:www.hbe.co.kr
- 8 -
HANBit Electronics Co.,Ltd.
REV.1.0 (August.2002)
SIMPLIFIED TRUTH TABLE
COMMAND
CKE
n-1
CKE
n
/C
S
/R
A
S
L
/C
A
S
L
/W
E
D
Q
M
X
BA
0,1
A10/
AP
A11
A9~A0
NOTE
Register
Mode register set
Auto refresh
H
X
H
L
L
L
OP code
1,2
3
3
3
3
Entry
H
L
L
L
H
X
X
L
H
L
H
X
L
H
X
H
H
X
H
Refresh
Self
refresh
Exit
L
H
X
X
Bank active & row addr.
H
X
X
V
Row address
Auto
disable
Auto
disable
precharge
L
4
Read &
column
address
precharge
H
X
L
H
L
H
X
V
H
Column
Address
(A0 ~ A9)
4,5
Auto
disable
precharge
L
Column
Address
(A0 ~ A9)
4
Write &
column
address
Auto
disable
precharge
H
X
L
H
L
L
X
V
H
4,5
Burst Stop
Precharg
e
H
X
L
L
H
L
X
X
6
Bank selection
All banks
V
X
L
H
H
X
L
L
H
L
X
X
H
L
X
H
L
H
L
X
V
X
X
H
X
V
X
V
X
X
H
X
V
X
V
X
X
H
X
V
Entry
H
L
X
Clock suspend or
active power down
Exit
L
H
X
X
Entry
H
L
X
Precharge
down mode
power
Exit
L
H
X
X
DQM
H
X
X
H
V
X
7
H
L
X
H
X
H
No operation command
H
X
X
X
(V=Valid, X=Don't care, H=Logic high, L=Logic low)
Notes :
1. OP Code : Operand code
A0 ~ A12 & BA0 ~ BA1 : Program keys. (@ MRS)
2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected.
If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
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