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參數(shù)資料
| 型號： | HM67S18258 |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 4M Synchronous Fast Static RAM (256k-words ×18-bits)(4M 同步快速靜態(tài)RAM (256k字 ×18位)) |
| 中文描述： | 4分同步快速靜態(tài)存儲器（256k -字× 18位）（4分同步快速靜態(tài)隨機存儲器（256k字× 18位）） |
| 文件頁數(shù)： | 15/24頁 |
| 文件大小： | 184K |
| 代理商： | HM67S18258 |
HM67S18258 Series
15
Boundary Scan Test Access Port Operations
overview
In order to perform the interconnect testing of the modules that include this SRAM, the serial boundary
access port (TAP) is designed to operate in a manner consistent with IEEE Standard 1149.1 - 1990. But
does not implement all of the functions required for 1149.1. the HM67S18258 contains a TAP controller.
Instruction resister, Boundary scan resister, Bypass and ID resister.
Test Access Port Pins
Symbol I/O
Name
TCK
Test Clock
TMS
Test Mode Select
TDI
Test Data In
TDO
Notes: This Device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. To disable
the TAP, TCK must be connected to V
SS
. TDO should be left unconnected.
Test Data Out
TAP DC Operating Characteristics
(Ta = 0
°
C to 70
°
C [Tj max = 110
°
C])
Parameter
Symbol
Min
Max
Note
Boundary scan Input High voltage
V
IH
V
IL
I
LI
V
OL
V
OH
2.0 V
V
DD
+ 0.3 V
0.8 V
Boundary scan Input Low voltage
–0.5 V
Boundary scan Input Leakage Current
–1
μ
A
+1
μ
A
1
Boundary scan Output Low voltage
0.4 V
2
Boundary scan Output High voltage
Notes: 1. 0
≤
Vin
≤
V
DD
2. I
OL
= 2 mA
3. I
OH
= –2 mA
2.4 V
3
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