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參數(shù)資料
| 型號(hào)： | HM62G36128 |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 4M Synchronous Fast Static RAM (128k-words ×36-bits)(4M同步快速靜態(tài)RAM(128k字 ×36位)) |
| 中文描述： | 4分同步快速靜態(tài)存儲(chǔ)器（128K的，字× 36位）（4分同步快速靜態(tài)隨機(jī)存儲(chǔ)器（128K的字× 36位）） |
| 文件頁數(shù)： | 8/23頁 |
| 文件大?。?/td> | 206K |
| 代理商： | HM62G36128 |
HM62G36128 Series
8
DC Characteristics
(Ta = 0 to 70
°
C, [Tjmax=110C], V
DD
= 3.3V+10%, –5%)
Parameter
Symbol
Min
Max
Unit
Note
Input Leakage Current
I
LI
I
LO
I
SBZZ
I
DD4
I
DD5
I
DD2
—
2
μ
A
μ
A
1
Output Leakage Current
—
5
2
Standby Current
—
100
mA
3
VDD Operating Current, excluding output drivers.
4ns cycle
—
580
mA
4
5ns cycle
—
500
mA
4
Quiescent Active Power Supply Current.
—
180
mA
5
Parameter
Symbol
Min
Typ
Max
Unit
Note
Output Low Voltage
V
OL
V
OH
RQ
V
SS
—
V
SS
+0.4
V
DDQ
350
V
6
Output High Voltage
V
DDQ
–0.4
150
—
V
6
ZQ pin Connect Resistance
250
Output “Low” Current
I
OL
I
OH
(V
DDQ
/2)/[(RQ/5)–15%]
(V
DDQ
/2)/[(RQ/5)+15%]
(V
DDQ
/2)/[(RQ/5)+15%]
(V
DDQ
/2)/[(RQ/5)–15%]
mA
7,9
Output “High” Current
Note:
1. 0
≤
Vin
≤
V
DDQ
for all input pins( except V
REF
,ZQ,M1,M2 pin)
2. 0
≤
VOUT
≤
V
DDQ
, DQ in High–Z
3. All inputs (except clock) are held at either VIH or VIL,ZZ is held at VIH,Iout=0 mA
4. Iout = 0 mA, read 50% / write 50%, V
DD
= V
DD
max , Frequency =min.cycle
5. Iout = 0 mA, read 50% / write 50%, V
DD
= V
DD
max , Frequency = 3 Mhz
6. Minimum impedance push pull output buffer mode, I
OH
=–6mA, I
OL
=6mA
7. Measured at V
OL
=1/2 V
DDQ
8. Measured at V
OH
=1/2 V
DDQ
9. Output buffer impedance can be programmed by terminating the ZQ pin to VSS through a
precision resister(RQ). The value of RQ is five times the output impedance desired. The
allowable range of RQ to guarantee impedance matching with a tolerance of 15% is between
150
and 350
. If the status of ZQ pin is open ,output impedance is maximum. Maximum
impedance occurs with ZQ connected to V
. The impedance update of the output driver
occurs when the SRAM is in High-Z. Write and Deselect operations will synchronously switch
the SRAM into and out of High-Z, therefore triggering an update. The user may choose to invoke
asynchronous
G
updates by providing a
G
setup and hold about the K clock to guarantee the
proper update. At power up, the output impedance default to minimum impedance. It will take
1024 cycles for the impedance to be completely updated if the programmed impedance is much
higher than minimum impedance.
mA
8,9
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