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參數(shù)資料
| 型號： | HM62864 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 65536-word ⅴ 8-bit High Speed CMOS Static RAM |
| 中文描述： | 65536字ⅴ8位高速CMOS靜態(tài)RAM |
| 文件頁數(shù)： | 13/15頁 |
| 文件大小： | 124K |
| 代理商： | HM62864 |
HM62864 Series
13
Low V
CC
Data Retention Characteristics
(Ta = 0 to +70
°
C)
This characteristics is guaranteed only for L-version.
Parameter
V
CC
for data retention
Symbol
V
DR
Min
2.0
Typ
*1
Max
5.5
Unit
V
Test conditions
*5
0 V
≤
Vin
≤
V
CC
, (1) or (2)
(1)
CS1
≥
V
CC
–
0.2 V,
CS2
≥
V
–
0.2 V
(2) 0 V
≤
CS2
≤
0.2 V
V
CC
= 3.0 V, 0 V
≤
Vin
≤
V
, (1) or (2)
(1)
CS1
≥
V
–
0.2 V, CS2
≥
V
CC
–
0.2V
(2) 0 V
≤
CS2
≤
0.2 V
—
Data retention current
I
CCDR
—
0.1
30
*2
μ
A
I
CCDR
t
CDR
—
0.1
10
*3
μ
A
Chip deselect to data
retention time
0
—
—
ns
See retention waveform
Operation recovery time
Notes: 1. Typical values are at V
CC
= 3.0 V, Ta = 25
°
C and not guaranteed.
2. 10
μ
A max at Ta = 0 to 40
°
C.
3. This characteristics guaranteed for only L-SL version. 3
μ
A max at Ta = 0 to 40
°
C.
4. t
RC
= Read cycle time.
5. CS2 controls address buffer,
WE
buffer,
CS1
buffer,
OE
buffer, and Din buffer. If CS2 controls
data retention mode, Vin levels (address,
WE
,
OE
,
CS1
, I/O) can be in the high impedance
state. If
CS1
controls data retention mode, CS2 must be CS2
≥
V
–
0.2 V or 0 V
≤
CS2
≤
0.2
V. The
other
input levels (address,
WE
,
OE
, I/O) can be in the high impedance state.
t
R
t
RC
*4
—
—
ns
Low V
CC
Data Retention Timing Waveform (1)
(
CS1
Controlled)
CC
V
4.5 V
2.2 V
V
0 V
CS1
t
CDR
t
R
CS1 V – 0.2 V
DR1
Data retention mode
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相關代理商/技術參數(shù) |
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| HM62864LFP-5SL | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
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| HM62864LFP-8 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
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