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參數(shù)資料
| 型號(hào)： | HM628512CLFP-5SL |
| 廠商： | Hitachi,Ltd. |
| 元件分類： | SRAM |
| 英文描述： | 4 M SRAM (512-kword x 8-bit) |
| 中文描述： | 四米的SRAM（512 - KWord的× 8位） |
| 文件頁(yè)數(shù)： | 12/17頁(yè) |
| 文件大?。?/td> | 84K |
| 代理商： | HM628512CLFP-5SL |
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HM628512C Series
12
Low V
CC
Data Retention Characteristics
(Ta = –20 to +70
°
C)
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions*
3
CS
≥
V
CC
– 0.2 V, Vin
≥
0 V
V
CC
= 3.0 V, Vin
≥
0 V
CS
≥
V
CC
– 0.2 V
V
CC
for data retention
Data retention current
V
DR
I
CCDR
2
—
—
V
—
1*
4
50*
1
μ
A
—
1*
4
15*
2
μ
A
Chip deselect to data retention time
t
CDR
t
R
0
—
—
ns
See retention waveform
Operation recovery time
Notes: 1. For L-version and 20
μ
A (max.) at Ta = –20 to +40
°
C.
2. For L-SL-version and 3
μ
A (max.) at Ta = –20 to +40
°
C.
3.
CS
controls address buffer,
WE
buffer,
OE
buffer, and Din buffer. In data retention mode, Vin
levels (address,
WE
,
OE
, I/O) can be in the high impedance state.
4. Typical values are at V
CC
= 3.0 V, Ta = +25
°
C and specified loading, and not guaranteed.
5. t
RC
= read cycle time.
t
RC
*
5
—
—
ns
Low V
CC
Data Retention Timing Waveform
(
CS
Controlled)
V
CC
4.5 V
2.2 V
V
DR
0 V
CS
t
CDR
t
R
CS
≥
V
CC
– 0.2 V
Data retention mode
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HM628512CLFP-5SLTR | 制造商:HITACHI 功能描述: 制造商:Hitachi 功能描述:512K X 8 STANDARD SRAM, 55 NS, PDSO32 |
| HM628512CLFP-7 | 制造商:Hitachi 功能描述: |
| HM628512CLFP-7SL | 制造商:Renesas Electronics Corporation 功能描述:SRAM Chip Async Single 5V 4M-Bit 512K x 8 70ns 32-Pin SOP |
| HM628512CLFPI-5 | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:Wide Temperature Range Version 4 M SRAM (512-kword ′ 8-bit) |
| HM628512CLFPI-7 | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:Wide Temperature Range Version 4 M SRAM (512-kword ′ 8-bit) |
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