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參數(shù)資料
| 型號： | HM628128DI |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 1 M SRAM (128-kword ×8-bit)(1M靜態(tài)RAM (128k字 ×8位)) |
| 中文描述： | 1個M的SRAM（128 - KWord的× 8位）（100萬靜態(tài)隨機存儲器（128K的字× 8位）） |
| 文件頁數(shù)： | 7/16頁 |
| 文件大?。?/td> | 75K |
| 代理商： | HM628128DI |
HM628128DI Series
7
AC Characteristics
(Ta = –40 to +85
°
C, V
CC
= 5.0 V
±
10%, unless otherwise noted.)
Test Conditions
Input pulse levels: V
IL
= 0.6 V, V
IH
= 2.4 V
Input rise and fall time: 5 ns
Input timing reference levels: 1.5 V
Output timing reference level: 1.5 V
Output load:1 TTL Gate+ CL (100 pF) (Including scope and jig)
Read Cycle
HM628128DI
-7
Parameter
Symbol
Min
Max
Unit
Notes
Read cycle time
t
RC
t
AA
t
ACS1
t
ACS2
t
OE
t
OH
t
CLZ1
t
CLZ2
t
OLZ
t
CHZ1
t
CHZ2
t
OHZ
70
—
ns
Address access time
—
70
ns
Chip select access time
—
70
ns
—
70
ns
Output enable to output valid
—
35
ns
Output hold from address change
10
—
ns
Chip selection to output in low-Z
10
—
ns
2, 3
10
—
ns
2, 3
Output enable to output in low-Z
5
—
ns
2, 3
Chip deselection to output in high-Z
0
25
ns
1, 2, 3
0
25
ns
1, 2, 3
Output disable to output in high-Z
0
25
ns
1, 2, 3
相關PDF資料 |
PDF描述 |
|---|---|
| HM628128DLFP-7 | 1 M SRAM (128-kword x 8-bit) |
| HM628128DLFP-7SL | 1 M SRAM (128-kword x 8-bit) |
| HM628128DLFP-7UL | Synchronous 4-Bit Up/Down Binary Counters 16-CDIP -55 to 125 |
| HM628128DLP-5 | Synchronous 4-Bit Up/Down Binary Counters 20-LCCC -55 to 125 |
| HM628128DLP-5SL | Synchronous 4-Bit Up/Down Binary Counters 16-CDIP -55 to 125 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HM628128DLFI7TR | 制造商:MITSUBISHI 功能描述:NEW |
| HM628128DLFP17 | 制造商:Hitachi 功能描述: |
| HM628128DLFP-5 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:1 M SRAM (128-kword x 8-bit) |
| HM628128DLFP-5SL | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:1 M SRAM (128-kword x 8-bit) |
| HM628128DLFP-5UL | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:1 M SRAM (128-kword x 8-bit) |
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