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參數(shù)資料
| 型號(hào)： | HM62256BLT-7SL |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | Triple 3-Input Positive-AND Gates 14-CFP -55 to 125 |
| 中文描述： | 256k的SRAM（32 KWord的× 8位） |
| 文件頁(yè)數(shù)： | 20/20頁(yè) |
| 文件大?。?/td> | 154K |
| 代理商： | HM62256BLT-7SL |
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HM62256B Series
20
Revision Record
(cont.)
Rev.
Date
Contents of Modification
Drawn by
Approved by
3.0
Jun. 19, 1995
AC Characteristics
t
PW
min: 30/35/40/50 ns to 20/25/30/35 ns
t
max: 25/30/35/40 ns to 20/20/25/30 ns
Low V
Data Retention Characteristics
Addition of note 4.
t
CCDR
typ: 0.2/0.2
μ
A to 0.05/0.05/0.05
μ
A
max: 30/10
μ
A to 30/10/3
μ
A
M. Higuchi
K. Yoshizaki
4.0
Nov. 29, 1995
Ordering Information (HM62256BLFP-4 Series)
Addition of note (Under development)
AC Characteristics
Test Conditions
HM62256-5/7/8:1TTL Gate + C
(100pF) to
HM62256-5:1TTL Gate + C
(50pF) and
HM62256-7/8:1TTL Gate + C
L
(100pF)
Change of format
Deletion of HM62256B-4 Series
M. Higuchi
K. Yoshizaki
5.0
Jul. 9, 1997
M. Higuchi
K. Imato
6.0
Nov. 13,1997
Operation Table
Correct Error
DC Operating Conditions
Correct Error
DC Characteristics
Correct Error
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HM62256BLT-8 | Triple 3-Input Positive-AND Gates 14-CDIP -55 to 125 |
| HM62256BLTM-5SL | Triple 3-Input Positive-AND Gates 20-LCCC -55 to 125 |
| HM62256BLTM-7SL | Triple 3-Input Positive-AND Gates 14-CDIP -55 to 125 |
| HM62256BLTM-7UL | Triple 3-Input Positive-AND Gates 14-CFP -55 to 125 |
| HM62256BLTM-8 | Dual J-K Negative-Edge-Triggered Flip-Flops With Preset And Clear 16-CDIP -55 to 125 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HM62256BLT-8 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:256k SRAM (32-kword x 8-bit) |
| HM62256BLTM-4SL | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
| HM62256BLTM-5SL | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:256k SRAM (32-kword x 8-bit) |
| HM62256BLTM-7SL | 制造商:Hitachi 功能描述:Static RAM, 32Kx8, 28 Pin, Plastic, TSSOP |
| HM62256BLTM-7UL | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:256k SRAM (32-kword x 8-bit) |
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