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參數(shù)資料
| 型號： | HM62256BLP-7SL |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | Triple 3-Input Positive-NAND Gates 14-CDIP -55 to 125 |
| 中文描述： | 256k的SRAM（32 KWord的× 8位） |
| 文件頁數(shù)： | 8/20頁 |
| 文件大小： | 154K |
| 代理商： | HM62256BLP-7SL |
HM62256B Series
8
Write Cycle
HM62256B
-5
-7
-8
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Unit
Notes
Write cycle time
t
WC
t
CW
t
AS
t
AW
t
WP
t
WR
t
WHZ
t
DW
t
DH
t
OW
t
OHZ
55
—
70
—
85
—
ns
Chip selection to end of write
40
—
60
—
75
—
ns
5
Address setup time
0
—
0
—
0
—
ns
6
Address valid to end of write
40
—
60
—
75
—
ns
Write pulse width
35
—
50
—
55
—
ns
4, 13
Write recovery time
0
—
0
—
0
—
ns
7
Write to output in high-Z
0
20
0
25
0
30
ns
1, 2, 8
Data to write time overlap
25
—
30
—
35
—
ns
Data hold from write time
0
—
0
—
0
—
ns
Output active from end of write
5
—
5
—
5
—
ns
2
Output disable to output in High-Z
Notes: 1. t
, t
and t
are defined as the time at which the outputs achieve the open circuit conditions
and are not referred to output voltage levels.
2. This parameter is sampled and not 100% tested.
3. Address must be valid prior to or simultaneously with
CS
going low.
4. A write occurs during the overlap of a low
CS
and a low
WE
. A write begins at the latest
transition of
CS
going low or
WE
going low. A write ends at the earliest transition of
CS
going
high or
WE
going high. t
WP
is measured from the beginning of write to the end of write.
5. t
CW
is measured from
CS
going low to the end of write.
6. t
AS
is measured from the address valid to the beginning of write.
7. t
WR
is measured from the earliest of
CS
or
WE
going high to the end of write cycle.
8. During this period, I/O pins are in the output state; therefore, the input signals of the opposite
phase to the outputs must not be applied.
9. If
CS
goes low simultaneously with
WE
going low or after
WE
going low, the outputs remain in
the high impedance state.
10.Dout is the same phase of the latest written data in this write cycle.
11.Dout is the read data of next address.
12.If
CS
is low during this period, I/O pins are in the output state. Therefore, the input signals of the
opposite phase to the outputs must not be applied to them.
13.In the write cycle with
OE
low fixed, t
WP
must satisfy the following equation to avoid a problem of
data bus contention.
t
WP
≥
t
DW
min + t
WHZ
max
0
20
0
25
0
30
ns
1, 2, 8
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HM62256BLSP-7 | Triple 3-Input Positive-NAND Gates 14-CFP -55 to 125 |
| HM62256BLSP-7SL | Triple 3-Input Positive-AND Gates 14-CDIP -55 to 125 |
| HM62256BLT-7SL | Triple 3-Input Positive-AND Gates 14-CFP -55 to 125 |
| HM62256BLT-8 | Triple 3-Input Positive-AND Gates 14-CDIP -55 to 125 |
| HM62256BLTM-5SL | Triple 3-Input Positive-AND Gates 20-LCCC -55 to 125 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HM62256BLPI-10 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
| HM62256BLPI-7SL | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
| HM62256BLSP10 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:IC-256K CMOS SRAM |
| HM62256BLSP-7 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:256k SRAM (32-kword x 8-bit) |
| HM62256BLSP-7SL | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:256k SRAM (32-kword x 8-bit) |
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