- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄370622 > HM5264805FLTT-B60 (Hitachi,Ltd.) 64M LVTTL interface SDRAM 133 MHz/100 MHz PDF資料下載
參數(shù)資料
| 型號(hào)： | HM5264805FLTT-B60 |
| 廠(chǎng)商： | Hitachi,Ltd. |
| 英文描述： | 64M LVTTL interface SDRAM 133 MHz/100 MHz |
| 中文描述： | 6400 LVTTL接口SDRAM的133 MHz/100 MHz的 |
| 文件頁(yè)數(shù)： | 20/67頁(yè) |
| 文件大?。?/td> | 870K |
| 代理商： | HM5264805FLTT-B60 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)當(dāng)前第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)
HM5264165F/HM5264805F/HM5264405F-75/A60/B60
20
Mode Register Configuration
The mode register is set by the input to the address pins (A0 to A13) during mode register set cycles. The
mode register consists of five sections, each of which is assigned to address pins.
A13, A12, A11, A10, A9, A8: (OPCODE):
The SDRAM has two types of write modes. One is the burst
write mode, and the other is the single write mode. These bits specify write mode.
Burst read and burst write:
Burst write is performed for the specified burst length starting from the column
address specified in the write cycle.
Burst read and single write:
Data is only written to the column address specified during the write cycle,
regardless of the burst length.
A7:
Keep this bit Low at the mode register set cycle. If this pin is high, the vender test mode is set.
A6, A5, A4: (LMODE):
These pins specify the
CAS
latency.
A3: (BT):
A burst type is specified. When full-page burst is performed, only "sequential" can be selected.
A2, A1, A0: (BL):
These pins specify the burst length.
A2 A1
A0
Burst length
BT=0
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
1
2
4
8
R
R
1
1
1
F.P.
BT=1
1
1
0
R
1
2
4
8
R
R
R
R
A3
0 Sequential
1
Interleave
Burst type
A6
0
0
0
0
1
A5
0
0
1
1
X
A4 CAS latency
0
1
0
1
X
R
R
2
3
R
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
OPCODE
0
LMODE
BT
BL
A9
0
0
1
1
R
Write mode
Burst read and burst write
A8
0
1
0
1
Burst read and single write
R
F.P. = Full Page
R is Reserved (inhibit)
X: 0 or 1
A11
A10
A10
X
X
X
A11
0
X
X
X
0
A12
A13
A13
0
X
X
X
A12
0
X
X
X
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HM5264405FLTT-B60 | 64M LVTTL interface SDRAM 133 MHz/100 MHz |
| HM5264805F | 64M LVTTL interface SDRAM(64M LVTTL接口同步DRAM) |
| HM5264165F | 64M LVTTL interface SDRAM(64M LVTTL接口同步DRAM) |
| HM5264165FLTT-75 | 64M LVTTL interface SDRAM 133 MHz/100 MHz |
| HM5264165FLTT-A60 | 64M LVTTL interface SDRAM 133 MHz/100 MHz |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HM5264805FTT-75 | 制造商:ELPIDA 制造商全稱(chēng):Elpida Memory 功能描述:64M LVTTL interface SDRAM 133 MHz/100 MHz 1-Mword × 16-bit × 4-bank/2-Mword × 8-bit × 4-bank /4-Mword × 4-bit × 4-bank PC/133, PC/100 SDRAM |
| HM5264805FTT-A60 | 制造商:ELPIDA 制造商全稱(chēng):Elpida Memory 功能描述:64M LVTTL interface SDRAM 133 MHz/100 MHz 1-Mword × 16-bit × 4-bank/2-Mword × 8-bit × 4-bank /4-Mword × 4-bit × 4-bank PC/133, PC/100 SDRAM |
| HM5264805FTT-B60 | 制造商:HITACHI 制造商全稱(chēng):Hitachi Semiconductor 功能描述:64M LVTTL interface SDRAM 133 MHz/100 MHz |
| HM5264805LTT-10 | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:x8 SDRAM |
| HM5264805LTT-80 | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:x8 SDRAM |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。