參數(shù)資料
型號: HM5225325F
廠商: Hitachi,Ltd.
英文描述: 256-Mbit SDRAM(256M位同步RAM)
中文描述: 256M的SDRAM(256M位同步內(nèi)存)
文件頁數(shù): 11/16頁
文件大?。?/td> 144K
代理商: HM5225325F
HM5225645F-B60, HM5225325F-B60
11
Notes: 1. I
depends on output load condition when the device is selected. I
CC
(max) is specified at the
output open condition.
2. One bank operation.
3. Input signals are changed once per one clock.
4. Input signals are changed once per two clocks.
5. Input signals are changed once per four clocks.
6. After power down mode, CLK operating current.
7. After power down mode, no CLK operating current.
8. After self refresh mode set, self refresh current.
9. Input signals are V
IH
or V
IL
fixed.
Capacitance
(Ta = 25
°
C, V
CC
= 3.3 V
±
0.3 V)
Parameter
Symbol
Min
Max
Unit
Notes
Input capacitance (CLK)
C
I1
C
I2
10
14
pF
1, 2, 4
Input capacitance
(Input except DQM)
10
14
pF
1, 2, 4
Input capacitance (DQM)
C
I3
C
O
2.5
5
pF
1, 2, 4
Output capacitance (DQ)
Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. Measurement condition: f = 1 MHz, 1.4 V bias, 200 mV swing.
3. DQMB = V
IH
to disable Dout.
4. This parameter is sampled and not 100% tested.
3
5
pF
1, 2, 3, 4
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