參數(shù)資料
型號(hào): HM5212325FBPC-B60
廠(chǎng)商: Hitachi,Ltd.
英文描述: 128M LVTTL interface SDRAM 100 MHz 1-Mword x 32-bit x 4-bank PC/100 SDRAM
中文描述: 128M的LVTTL接口SDRAM的100兆赫1 - Mword × 32位× 4個(gè)銀行PC/100 SDRAM的
文件頁(yè)數(shù): 1/13頁(yè)
文件大小: 58K
代理商: HM5212325FBPC-B60
HM5212325FBPC-B60
128M LVTTL interface SDRAM
100 MHz
1-Mword
×
32-bit
×
4-bank
PC/100 SDRAM
ADE-203-1122C (Z)
Rev. 1.0
May. 12 , 2000
Description
The Hitachi HM5212325FBPC is a 128-Mbit SDRAM organized as 1048576-word
×
32-bit
×
4-bank. All
inputs and outputs are referred to the rising edge of the clock input. It is packaged in standard 90-bump fine
pitch BGA.
Features
Single chip wide bit solution (
×
32)
3.3 V power supply
Clock frequency: 100 MHz (max)
LVTTL interface
Extremely small foot print: 0.8 mm pitch
Package: FBGA (BP-90)
4 banks can operate simultaneously and independently
Burst read/write operation and burst read/single write operation capability
Programmable burst length: 4/8/full page
2 variations of burst sequence
Sequential (BL = 4/8/full page)
Interleave (BL = 4/8)
Programmable
CAS
latency: 2/3
Byte control by DQMB
Refresh cycles: 4096 refresh cycles/64 ms
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