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參數(shù)資料
| 型號(hào)： | HM51W18165LTT-7 |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | x16 EDO Page Mode DRAM |
| 中文描述： | x16 EDO公司頁(yè)面模式的DRAM |
| 文件頁(yè)數(shù)： | 17/36頁(yè) |
| 文件大小： | 461K |
| 代理商： | HM51W18165LTT-7 |
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HM51W16165 Series, HM51W18165 Series
17
Notes concerning 2
CAS
control
Please do not separate the
UCAS
/
LCAS
operation timing intentionally. However skew between
UCAS
/
LCAS
are allowed under the following conditions.
1. Each of the
UCAS
/
LCAS
should satisfy the timing specifications individually.
2. Different operation mode for upper/lower byte is not allowed; such as following.
RAS
UCAS
LCAS
WE
Delayed write
Early write
3. Closely separated upper/lower byte control is not allowed. However when the condition (t
CP
≤
t
UL
) is
satisfied, EDO page mode can be performed.
RAS
UCAS
LCAS
tUL
4. Byte control operation by remaining
UCAS
or
LCAS
high is guaranteed.
This Material Copyrighted By Its Respective Manufacturer
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HM51W18165J-5 | 16 M EDO DRAM (1-Mword 16-bit) 4 k Refresh/1 k Refresh |
| HM51W16165J-6 | 16 M EDO DRAM (1-Mword 16-bit) 4 k Refresh/1 k Refresh |
| HM51W16165LJ-7 | 16 M EDO DRAM (1-Mword 16-bit) 4 k Refresh/1 k Refresh |
| HM51W18165LJ-7 | 16 M EDO DRAM (1-Mword 16-bit) 4 k Refresh/1 k Refresh |
| HM51W18165J-6 | 16 M EDO DRAM (1-Mword 16-bit) 4 k Refresh/1 k Refresh |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HM51W4260CLTT-6 | 制造商:Hitachi 功能描述: |
| HM5212165/2805 | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Series 128M LVTTL Interface SDRAM 66 MHz 2-Mword X 16-Bit X4-Bank |
| HM5212165D/2805D | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Series 128M LVTTL Interface SDRAM 100 MHz 2-Mword X 16-Bit X 4- |
| HM5212165D/2805D-B60 | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:128M LVTTL Interface SDRAM 100 MHz 2-Mword X 16-Bit X 4-Ban |
| HM5212165D/805D-A60 | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:128M LVTTL Interface SDRAM 100 MHz 2-Mword X 16-Bit X 4-Bank |
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