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參數(shù)資料
| 型號： | HM51W16165LTT-6 |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | x16 EDO Page Mode DRAM |
| 中文描述： | x16 EDO公司頁面模式的DRAM |
| 文件頁數(shù)： | 15/36頁 |
| 文件大?。?/td> | 461K |
| 代理商： | HM51W16165LTT-6 |
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HM51W16165 Series, HM51W18165 Series
15
Self Refresh Mode
(L-version)
HM51W16165L/HM51W18165L
-5
-6
-7
Parameter
RAS
pulse width (self refresh)
Symbol
Min
Max
Min
Max
Min
Max
Unit
Notes
t
RASS
100
—
100
—
100
—
μ
s
28, 29, 30,
31
RAS
precharge time (self refresh)
CAS
hold time (self refresh)
Notes: 1. AC measurements assume t
T
= 2 ns.
2. An initial pause of 200
μ
s is required after power up followed by a minimum of eight initialization
cycles (any combination of cycles containing
RAS
-only refresh or
CAS
-before-
RAS
refresh).
3. Operation with the t
(max) limit insures that t
(max) can be met, t
(max) is specified as a
reference point only; if t
RCD
≥
t
RAD
(max) + t
AA
(max) – t
CAC
(max), then access time is controlled
exclusively by t
CAC
.
4. Operation with the t
(max) limit insures that t
(max) can be met, t
(max) is specified as a
reference point only; if t
is greater than the specified t
RAD
(max) limit, then access time is
controlled exclusively by t
AA
.
5. Either t
OED
or t
CDD
must be satisfied.
6. Either t
DZO
or t
DZC
must be satisfied.
7. V
(min) and V
(max) are reference levels for measuring timing of input signals. Also, transition
times are measured between V
IH
(min) and V
IL
(max).
8. Assumes that t
≤
t
(max) and t
≤
t
RAD
(max). If t
or t
is greater than the maximum
recommended value shown in this table, t
RAC
exceeds the value shown.
9. Measured with a load circuit equivalent to 1 TTL loads and 100 pF.
10.Assumes that t
RCD
≥
t
RCD
(max) and t
RCD
+ t
CAC
(max)
≥
t
RAD
+ t
AA
(max).
11.Assumes that t
RAD
≥
t
RAD
(max) and t
RCD
+ t
CAC
(max)
≤
t
RAD
+ t
AA
(max).
12.Either t
RCH
or t
RRH
must be satisfied for a read cycles.
13.t
(max) and t
(max) define the time at which the outputs achieve the open circuit condition
and are not referred to output voltage levels.
14.t
, t
, t
, t
and t
are not restrictive operating parameters. They are included in the
data sheet as electrical characteristics only; if t
≥
t
(min), the cycle is an early write cycle
and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if t
RWD
≥
t
RWD
(min), t
≥
t
(min), and t
≥
t
(min), or t
≥
t
(min), t
≥
t
(min) and t
≥
t
(min), the cycle is a read-modify-write and the data output will contain data read from the
selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out
(at access time) is indeterminate.
15.These parameters are referred to
UCAS
and
LCAS
leading edge in early write cycles and to
WE
leading edge in delayed write or read-modify-write cycles.
16.t
RASP
defines
RAS
pulse width in EDO page mode cycles.
17.Access time is determined by the longest among t
AA
, t
CAC
and t
CPA
.
18.In delayed write or read-modify-write cycles,
OE
must disable output buffer prior to applying data
to the device
19.When both
UCAS
and
LCAS
go low at the same time, all 16-bit data are written into the device.
UCAS
and
LCAS
cannot be staggered within the same write/read cycles.
20 All the V
CC
and V
SS
pins shall be supplied with the same voltages.
t
RPS
t
CHS
90
—
110
—
130
—
ns
–50
—
–50
—
–50
—
ns
This Material Copyrighted By Its Respective Manufacturer
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| HM51W18165J-5 | 16 M EDO DRAM (1-Mword 16-bit) 4 k Refresh/1 k Refresh |
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