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參數(shù)資料
| 型號： | HM18TS402 |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | 顯示驅動器 |
| 英文描述： | LIQUID CRYSTAL DISPLAY DRIVER, UUC544 |
| 文件頁數(shù)： | 6/24頁 |
| 文件大?。?/td> | 219K |
| 代理商： | HM18TS402 |
HM18TS402
5. FUNCTIONAL DESCRIPTIONS
- 6 -
Preliminary
5.1 Data Input
DI/O,DO/I = “H” is loaded into the address shift register on the rising edge of CPH(n).
18bit(6bit x X,Y,Z) data are loaded into sampling register on the rising edge of CPH(n+1).
When LOAD = ”H” after the rising edge of CPH(n+134), the data in each sampling register
are transferred to hold register and the HM18TS402 outputs analog voltage signal through output buffer.
5.2 Extension of Output
By cascade connection of this device, Enlargement of driving data is available and as a result
it can be used to a larger size screen.
(1) U/D = “L”
DI/O pin of the former chip is connected to DO/I pin of the next chip.
The other input pins except DI/O and DO/I is connected commonly to each device.
(2) U/D = “H”
DO/I pin of the former chip is connected to DI/O pin of the next chip.
The other input pins except DO/I and DI/O is connected commonly to each device.
5.3 Gray-Scale Data Bus Relationship
The relationship between GS1/2, gray-scale number and color number.
Mode setting
Valid gray-scale data bus
GS1
GS2
Gray-scale
Data bus
Display
color
nIN5
nIN4
nIN3
nIN2
nIN1
nIN0
0
0
6 bit mode
262,144
Valid
0
1
4 bit mode
4,096
Valid
L/H
L/H
1
0
3 bit mode
512
Valid
L/H
L/H
L/H
1
1
1 bit mode
8
Valid
L/H
L/H
L/H
L/H
L/H
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