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參數(shù)資料
| 型號(hào)： | HM1-65262B-9 |
| 廠商： | INTERSIL CORP |
| 元件分類： | SRAM |
| 英文描述： | 16K x 1 Asynchronous CMOS Static RAM |
| 中文描述： | 16K X 1 STANDARD SRAM, 70 ns, CDIP20 |
| 封裝： | CERAMIC, DIP-20 |
| 文件頁(yè)數(shù)： | 6/7頁(yè) |
| 文件大?。?/td> | 41K |
| 代理商： | HM1-65262B-9 |
6-6
Low Voltage Data Retention
Intersil CMOS RAMs are designed with battery backup in
mind. Data retention voltage and supply current are guaran-
teed over temperature. The following rules ensure data
retention:
1. Chip Enable (E) must be held high during data retention;
within V
CC
to V
CC
+0.3V.
2. On RAMs which have selects or output enables (e.g., S,
G), one of the selects or output enables should be held in
the deselected state to keep the RAM outputs high
impedance, minimizing power dissipation.
3. Inputs which are to be held high (e.g., E) must be kept
between V
CC
+0.3V and 70% of V
CC
during the power
up and down transitions.
4. The RAM can begin operation > 55ns after V
CC
reaches
the minimum operating voltage (4.5V).
NOTE:
1. In this mode, W rises after E. If W falls before E by a time exceeding TWLQZ (Max) TELQX (Min), and rises after E by a time exceeding
TEHQZ (Max) TWHQZ (Min), then Q will remain in the high impedance state throughout the cycle.
FIGURE 4. WRITE CYCLE 2: CONTROLLED BY E (EARLY WRITE)
Timing Waveforms
(Continued)
(8) TAVAX
(20) TAVEH
E
W
D
Q
(21) TELEH
(22) TWLEH
(23) TDVEH
(19) TEHAX
(16) TWHQX
(24)
TEHDX
(4) TELQX
(15) TWLQZ
(7) TEHQZ
A
(18) TAVEL
V
CC
≥
2.0V
4.5V
4.5V
V
CC
>55ns
V
CC
-0.3V TO V
CC
+0.3V
DATA RETENTION
MODE
E
FIGURE 5. DATA RETENTION TIMING
HM-65262
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相關(guān)代理商/技術(shù)參數(shù) |
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| HM1-65262B-9+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x1 SRAM |
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| HM1-65262C-9 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x1 SRAM |
| HM1-65262C-9+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x1 SRAM |
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