參數(shù)資料
型號: HM-6518
廠商: Intersil Corporation
英文描述: 1024 x 1 CMOS RAM
中文描述: 1024 × 1 CMOS存儲器
文件頁數(shù): 6/9頁
文件大小: 220K
代理商: HM-6518
6-90
In the HM-6518/883 read cycle the address information is
latched into the on chip registers on the falling edge of E
(T = 0). Minimum address setup and hold time require-
ments must be met. After the required hold time the
addresses may change state without affecting device oper-
ation. In order for the output to be read S1, S2 and E must
be low, W must be high. When E goes high the output data
is latched into an on chip register. Taking either or both S1
or S2 high, forces the output buffer to a high impedance
state. The output data may be re-enabled at any time by
taking S1 and S2 low. On the falling edge of E the data will
be unlatched.
Timing Waveforms
TRUTH TABLE
TIME
REFERENCE
INPUTS
OUTPUTS
FUNCTION
E
S1
W
A
D
Q
-1
H
H
X
X
X
Z
Memory Disabled
0
X
H
V
X
Z
Cycle Begins, Addresses are Latched
1
L
L
H
X
X
X
Output Enabled
2
L
L
H
X
X
V
Output Valid
3
L
H
X
X
V
Output Latched
4
H
H
X
X
X
Z
Device Disabled, Prepare for Next Cycle
(Same as -1)
5
X
H
V
X
Z
Cycle Ends, Next Cycle Begins
(Same as 0)
NOTE: 1. Device selected only if both S1 and S2 are low, and deselected if either S1 or S2 are high.
TIME
REFERENCE
(8) TAVEL
TELAX
(9)
(8) TAVEL
NEXT
TELEL (17)
TEHEL (7)
TELEH (6)
TEHEL (7)
TWLEH (13)
TWLWH (16)
VALID DATA
TDVWH (10)
TWHDX (11)
HIGH Z
-1
0
1
2
3
4
5
A
E
W
D
Q
VALID
FIGURE 2. WRITE CYCLE
TELWH (15)
TWLSH (12)
TSLWH (14)
S1,
S2
HM-6518/883
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