參數(shù)資料
型號(hào): HIP9022AM
廠商: INTERSIL CORP
元件分類: 其它接口
英文描述: Dual High Speed Laser Driver
中文描述: SPECIALTY INTERFACE CIRCUIT, PQCC68
封裝: PLASTIC, MS-018AE, LCC-68
文件頁(yè)數(shù): 3/10頁(yè)
文件大?。?/td> 98K
代理商: HIP9022AM
4-3
Pin Descriptions
PIN
NUMBER
SYMBOL
DESCRIPTION
1, 2
ESD LASER GND
Laser supply and system ground.
3, 4, 5
ESD SHUNT DRAIN-1 Laser diode ESD protection.
6, 7
SD LASER PS-1
Laser power supply ESD protection.
8
V
DD
Input for 12V power supply.
9
NC
No connection.
10
VUP1
Filter capacitor for internally generated shunt gate upper voltage level (1
μ
F).
11
SG_1
Drive output to shunt Power FET gate.
12
VLOW1
Filter capacitor for internally generated shunt Power FET gate lower drive voltage level (1
μ
F).
13
V
EE
Input for -5V power supply.
14
GNDA1
Analog Ground.
15
GNDD1
Digital Ground.
16
CC1
Gate drive to the current source Power FET.
17
XTEN1+
Times 10 constant current monitor amplifier input from the high side of the sense resistor.
18
XTEN1-
Times 10 constant current monitor amplifier input from the low side of the sense resistor.
19
CTC1-10K
Thermal compensation short time constant where T
TC
= External C x 10k
. (External C typically equal
0.02
μ
F).
20
CTC1-27K
Thermal compensation long time constant where T
TC
= External C x 27k
. (External C typically equal
0.1
μ
F).
21
LASERON1B
Input control turns shunt Power FET gate drive ON/OFF with 5V CMOS logic. Low turns the shunt Power
FET OFF and the Laser ON. These pins have an internal pull-up.
22
OC1
Laser over-current indicator flag.
23
TECFB1
Feedback to stabilize the TEC loop.
24
TECREF1
Feedback to stabilize the TEC loop.
25
TECGDR1
Thermo-Electric Cooler Power FET gate drive.
26
TRES1
Thermo-Resistor output to ground connection for TEC control.
27
OT1
Laser out of temperature range indication.
28
NC
No connection.
29
INVERT
High input converts to operation with Pmos Current source and NDmos shunt Power FET external
transistors. Low input converts to operation with NDmos Current source and Pmos high side shunt Power
FET external transistors. This pin has an internal pull-down.
30
RESETB
When RESETB is held low, three reset actions occur. The LASERONB input is defeated to a Laser Off con-
dition. The SG_1, 2 outputs are switched to VLOW when in the INVERT low mode and to VUP when in the
INVERT high mode. The TEC amplifier is turned off to switch the TECGDR1, 2 outputs to Ground. This pin
has an internal pull-down.
31
DIAGINB
Low level activates the diagnostic mode. This pin has an internal pull-up.
32
NULLB
Auto-zeros the S/H amplifier selected by address when held low. This pin has an internal pull-up.
33
SB_H
Samples the selected address when held low. The setup time for address is <25ns. This pin has an internal
pull-up.
34
NC
No connection.
35
V
IN
Analog voltage sampled by selected S/H. The input voltage range is 0 to 5V. There is an internal voltage
clamp for voltage outside of this range. There is an internal 2 - 3
μ
s filter for noise rejection.
36
V
CC
Input for 5V power supply.
37
A3
Refer to the Table 1 Address Map. The A3 - A0 pins have an internal pull-up.
HIP9022
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