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參數(shù)資料
| 型號： | HIP9021IB |
| 廠商： | INTERSIL CORP |
| 元件分類： | 功率晶體管 |
| 英文描述： | Portable Battery Drive/Torque Controller for N-Channel MOSFETs in Motor Control Systems |
| 中文描述： | 0.018 A BUF OR INV BASED MOSFET DRIVER, PDSO8 |
| 封裝： | PLASTIC, MS-012-AA, SOIC-8 |
| 文件頁數(shù)： | 6/7頁 |
| 文件大?。?/td> | 59K |
| 代理商： | HIP9021IB |
6
Functional Description
Oscillator
The Oscillator triangle waveform is generated by the charge
and discharge of a 1nF external capacitor connected to the
OSC pin. The OSC terminal has a source and sink drive from a
current mirror which delivers
±
25
μ
A. The charge and discharge
of the external capacitor is controlled by 2 comparators which
compare respectively V
OSC
with 2/3 V
DD
and V
OSC
with 1/3
V
DD
. The period of the triangle wave is nominally 200
μ
s.
Gate Driver
The TRIGGER input signal is compared from the triangle
waveform of the oscillator to produce a square wave signal.
The duty cycle of the GATE drive signal is increased as the
TRIGGER input level increases. The output of the compara-
tor is then NANDed with a GATE Control signal which can
enable or disable the GATE output. The NAND gate output is
buffered to deliver 18mA typical GATE drive current.
Torque Effect
The triangle signal, after going through a divider, is also
compared with TRIGGER input level. This produces another
square wave of the same period but with a duty-cycle that is
smaller than the GATE by ~5%. This square wave is used to
enable the comparison between DRAIN and TORQUE
inputs while the MOSFET is conducting.
A torque effect condition exists when 80% of the DRAIN sig-
nal is higher than the TORQUE input level set voltage of the
potentiometer. During this time, the external delay capacitor of
3.3
μ
F is charged through an internal 100K resistor. When the
voltage at the DELAY pin reaches 0.25 x V
DD
, the RS flip-flop
is then set and the Gate Control (GC) signal shown in Figure
3 goes to low. The Output GATE drive signal is then disabled.
This situation remains even if the voltage on the DELAY pin
stays under 0.25 x V
DD
for a sustained period of time.
At the same time, when the RS flip-flop is set, the external
capacitor at the DELAY pin is discharged via the nMOS
device, Q2 which is driven by the Q output of the flip-flop.
Power-On Reset (POR)
In reference to Figure 3, the power on of the chip will cause
the reset of the RS Gate Control flip-flop when Q1 is
switched low. As an initial condition, the Gate Control (GC)
signal is reset high. Since power on is the only way to reset
the RS flip-flop, a disabled GATE drive signal due to a torque
effect condition requires a switched (trigger) reset.
The POR (power on reset) threshold requires that V
DD
be less
than 2V to initiate a reset. The POR circuit is based on the
behavior of the voltage reference cell that produces a constant
1.15V (REF. BIAS) when V
DD
is over 2V. When Q1 is forward
biased, the Q1 drain voltage goes low to reset the input of the
RS flip-flop.
GATE
2K
40K
BUF
OSC
TRIGGER
OSC
GATE
CONTROL
(GC)
φ
φ
1nF
+
-
1.15V
2K
6K
S
R
Q
Q
Q2
Q1
V
DD
+
-
DELAY
100K
50K
200K
330K
φ
φ
φ
φ
DRAIN
TORQUE
3.3
μ
F
PULL
REF.
LOAD
COMP
DELAY
COMP
15K
POR
MOTOR
V
BATT
150K
POWER
MOSFET
FIGURE 3. DETAILED LOGIC DIAGRAM OF THE PORTABLE DRIVE/TORQUE CONTROLLER FOR N-CHANNEL POWER MOSFETS
SHOWING THE DRAIN AND TORQUE, THE GATE CONTROL LOGIC AND THE TRIGGER (SPEED) CONTROL.
+
-
+
-
HIP9021
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