1
HIP9011
Engine Knock Signal Processor
The HIP9011 is used to provide a method of detecting
premature detonation often referred to as “Knock or Ping” in
internal combustion engines.
The IC is shown in the Simplified Block Diagram. The chip
can select between one of two sensors, if needed for
accurate monitoring or for “V” type engines. Internal control
via the SPI bus is fast enough to switch sensors between
each firing cycle. A programmable bandpass filter
processes the signal from either of the sensor inputs. The
bandpass filter can be selected to optimize the extraction
the engine knock or ping signals from the engine
background noise. Further single processing is obtained by
full wave rectification of the filtered signal and applying it to
an integrator whose output voltage level is proportional to
the knock signal amplitude. The chip is under
microprocessor control via a SPI interface bus.
Features
Two Sensor Inputs
Microprocessor Programmable
Accurate and Stable Filter Elements
Digitally Programmable Gain
Digitally Programmable Time Constants
Digitally Programmable Filter Characteristics
On-Chip Crystal Oscillator
Programmable Frequency Divider
External Clock Frequencies up to 24MHz
- 4, 5, 6, 8, 10, 12, 16, 20, and 24MHz
Operating Temperature Range -40oC to 125oC
Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
Engine Knock Detector Processor
Analog Signal Processing Where Controllable Filter
Characteristics are Required
Simplified Block Diagram
Ordering Information
PART
NUMBER
PART
MARKING
TEMP.
RANGE
(oC)
PACKAGE
PKG.
DWG. #
HIP9011AB
-40 to 125 20 Ld SOIC
M20.3
HIP9011ABZ
(See Note)
HIP9011ABZ
-40 to 125 20 Ld SOIC
(Pb-free)
M20.3
Add “T” suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
INTOUT
PROGRAMMABLE
2
- 0.111
RECTIFIER
PROGRAMMABLE
INTEGRATOR
40
- 600s
32 STEPS
OUTPUT
DRIVER
A
N
TIALIA
SING
FIL
T
E
R
3RD
ORDER
CHANNEL
S
E
LECT
S
W
ITCHES
PROGRAMMABLE
BANDPASS
FILTER
1
-20kHz
64 STEPS
REGISTERS
AND
STATE MACHINE
STAGE
TO SWITCHED
CAPACITOR
NETWORKS
SCK
CS
SI
SO
INT/HOLD
TEST
OSCIN
OSCOUT
VMID
CH0FB
CH0IN
CH1FB
CH1IN
VDD GND
POWER SUPPLY
AND
BIAS CIRCUITS
DIVIDER
PROGRAMMABLE
CH0NI
CH1NI
SAMPLE
AND HOLD
AND
ACTIVE
FULL WAVE
64 STEPS
GAIN
-
+
-
+
CLOCK
SPI
INTERFACE
Data Sheet
January 6, 2006
FN4367.2
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
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