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參數(shù)資料
| 型號(hào)： | HIP7020AP |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | 網(wǎng)絡(luò)接口 |
| 英文描述： | FPGA 2000000 SYSTEM GATE 1.8 VOLT - NOT RECOMMENDED for NEW DESIGN |
| 中文描述： | DATACOM, INTERFACE CIRCUIT, PDIP8 |
| 文件頁(yè)數(shù)： | 8/11頁(yè) |
| 文件大?。?/td> | 81K |
| 代理商： | HIP7020AP |
8
Low Pass Filter Input
The bus input has an on-chip input filter to strip off the
unwanted incoming high frequency noise. The 3dB point of
this filter is nominally 750kHz.
Diagnostic Bus-Isolated Loop-Back
An on-chip Bus-Isolated Diagnostic Loop-Back function is
controlled by the LB EN pin. The Loop-Back function is a mode
switch that is enabled by placing a logic low on the LB EN pin.
When activated, the signal flow is cross-switched to open the
Bus Receive Input and connect the Voltage Reference,
V
REF
output to the input of the Bus Receiver. This “Loops-
Back” the TX signal to the RX output while maintaining isola-
tion from the signal on the J1850 Bus. When the Loop-Back
is enabled, diagnostic trouble shooting can be done at each
individual node regardless of fault conditions on the bus.
Thermal Shut Down Protection
On-chip Thermal Shutdown Protection is designed to shut-
down source drive to the J1850 bus and protect the Bus
Transceiver IC output. The temperature shutdown threshold is
set to protect the absolute maximum junction temperature of
the chip and is nominally set for 160
o
C with 10
o
C of hystere-
sis. Thermal shutdown may occur when overload conditions
exist on the bus. (See Function Blocks - Thermal Shutdown.)
Package Pinout
BATT
The BATT pin is connected directly to the vehicle Battery
(Ignition) line. The Battery supply connection (V
BATT
) pro-
vides voltage for all on-chip functions, including the voltage
reference. As such, the BATT input is designed to withstand
transient power supply conditions.
NOTE:
Refer to SAE J1850, Table 5 for definition of Tv_ time duration definitions. i.e. By Definition a Short pulse = Tv1: t
TX(NOM)
= t
RX(NOM)
= 64
μ
s.
FIGURE 5. J1850 BUS WAVEFORM
FIGURE 6. PROPAGATION TIME DELAYS
50% = 3.875V
50%
100% = 7.75V
1.5V
V
BOH(MIN)
V
BOL(MAX)
8
μ
s
16
μ
s
t
f
8
μ
s
6.25V
8
μ
s
16
μ
s
t
r
TX GOES
LOW
Tv_
(NOTE)
8
μ
s
TRANSMIT
(TX)
J1850
BUS
RECEIVE
(RX)
50% VOLT LEVEL
50% VOLT LEVEL
t
DTXHBO
t
DTXLBO
t
DRXON
t
DRXOFF
3.875V
3.875V
Tv_
Tv_
Tv_
Tv_
Tv_
Tv_
HIP7020
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HIP7030A0 | J1850 8-Bit 68HC05 Microcontroller Emulator Version |
| HIP7030A0M | FPGA - 200000 SYSTEM GATE 2.5 VOLT - NOT RECOMMENDED for NEW DESIGN |
| HIP7030A2 | FPGA - 200000 SYSTEM GATE 2.5 VOLT - NOT RECOMMENDED for NEW DESIGN |
| HIP7030A2M | FPGA - 200000 SYSTEM GATE 2.5 VOLT - NOT RECOMMENDED for NEW DESIGN |
| HIP7030A2P | FPGA - 200000 SYSTEM GATE 2.5 VOLT - NOT RECOMMENDED for NEW DESIGN |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HIP7030A0 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:J1850 8-Bit 68HC05 Microcontroller Emulator Version |
| HIP7030A0M | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:J1850 8-Bit 68HC05 Microcontroller Emulator Version |
| HIP7030A2 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:J1850 8-Bit 68HC05 Microcontroller |
| HIP7030A2M | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:J1850 8-Bit 68HC05 Microcontroller |
| HIP7030A2P | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:J1850 8-Bit 68HC05 Microcontroller |
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